AK4584_01 Datasheet, PDF (50/53 Pages) Asahi Kasei Microsystems – 24Bit 96kHz Audio CODEC with DIT/DIR

ASAHI KASEI
[AK4584]
SYSTEM DESIGN
Figure 18 shows the system connection diagram. An evaluation board is available which demonstrates application circuits,
the optimum layout, power supply arrangements and measurement results.
[Measurement Condition]
• TVDD = 3.0V, Master mode, XTALE = “H”, DMCK = “L”
S/PDIF
sources
Shield
10µ
0.1µ
Analog 5V
5.1
10µ
13k
0.1µ
5.1
44 43 42 41 40 39 38 37 36 35 34
Shield
Shield
PDN Control
µP
1 TEST2
2 RX3
3 NC
4 RX4
5 PDN
6 INT0
7 INT1
8 CDTI
9 CDTO
10 CCLK
11 CSN
AK4584
ROUT 33
LOUT 32
VCOM 31
DZF 30 ^0.1µ
M/S 29
LRCK 28
BICK 27
SDTI 26
SDTO 25
MCKO2 24
MCKO1 23
MUTE
MUTE
2.2µ
Audio
DSP
12 13 14 15 16 17 18 19 20 21 22
0.1µ 0.1µ
C
C
10µ 10µ
S/PDIF out
Digital 3V
Note:
- X’tal Oscillation circuit is specified from 11.2896MHz to 24.576MHz. Capacitors “C” depend on the X’tal.
- AGND and DGND of the AK4584 should be distributed separately from the ground of external digital devices
(MPU, DSP etc.).
- When LOUT/ROUT drives a capacitive load, resistors should be added in series between LOUT/ROUT
and capacitive load.
- All input pins except pull-down pin (TEST1,2 pins) should not be left floating.
- To prevent coupling of TEST1, TEST2 and the RX signals, NC pins are connected PVSS.
Figure 18. Typical Connection Diagram
MS0118-E-00
- 50 -
2001/11