AK4584_01 Datasheet, PDF (35/53 Pages) Asahi Kasei Microsystems – 24Bit 96kHz Audio CODEC with DIT/DIR

ASAHI KASEI
[AK4584]
„ Reset and Power Down
The AK4584 has both a power-down mode for all circuits by pulling the PDN pin or a partial power-down mode that is
enabled via an internal register (see Table 22). The AK4584 should be reset once by bringing PDN pin = “L” upon
power-up.
PDN pin
L
H
PWDITN
x
0
x
x
x
x
x
PWVRN
x
x
0
x
x
x
x
PWADN PWDAN CM1-0
Function
x
x
x
All Power-down
x
x
x
DIT Power-down
x
x
x VREF Power-down
0
x
x ADC Power-down
x
0
x DAC Power-down
x
x
00 X’tal Power-down
x
x
01 PLL Power-down
Table 22. Reset & Power Down
Register Initialization
Yes
No
No
No
No
No
No
„ Serial Control Interface
The internal registers may be either written or read by the 4-wire µP interface pins: CSN, CCLK, CDTI & CDTO. The data
on this interface consists of Chip address (2bits, C1/0 are fixed to “00”), Read/Write (1bit), Register address (MSB first,
5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is clocked
out on the falling edge. For write operations, data is latched after the 16th rising edge of CCLK, after a high-to-low
transition of CSN. For read operations, the CDTO output goes to high impedance after a low-to-high transition of CSN.
The maximum speed of CCLK is 5MHz. The chip address is fixed to “00”. The access to the chip address except for “00”
is invalid. PDN pin = “L” resets the registers to their default values.
CSN
CCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CDTI
Write
CDTO
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
CDTI
Read
CDTO
C1 C0 R/W A4 A3 A2 A1 A0
Hi-Z
D7 D6 D5 D4 D3 D2 D1 D0 ^Hi-Z
C1 - C0 : Chip Address (Fixed to "00")
R/W : READ / WRITE ("1" : WRITE, "0" : READ)
A4 - A0 : Register Address
D7 - D0 : Control Data
Figure 17. Control I/F Timing
MS0118-E-00
- 35 -
2001/11