AK4584_01 Datasheet, PDF (12/53 Pages) Asahi Kasei Microsystems – 24Bit 96kHz Audio CODEC with DIT/DIR

ASAHI KASEI
SWITCHING CHARACTERISTICS
(Ta=−10 ∼ 70°C; AVDD, DVDD, PVDD=4.75 ∼ 5.25V, TVDD=2.7 ∼ 5.25V; C_L=20pF)
Parameter
Symbol
min
typ
Master Clock Timing
Crystal Resonator Frequency
11.2896
External Clock
Frequency
fCLK
11.2896
Pulse Width Low
tCLKL 0.4/fCLK
Pulse Width High tCLKH 0.4/fCLK
MCKO1 Output
Frequency
fMCK 11.2896
Duty Cycle (Note 15) dMCK
40
50
MCKO2 Output
Frequency
fMCK
5.6448
Duty Cycle
dMCK
40
50
PLL Clock Recover Frequency
fPLL
32
LRCK Frequency
Normal Speed Mode (DFS0=“0”, DFS1=“0”)
fsn
32
Double Speed Mode (DFS0=“1”, DFS1=“0”)
fsd
88.2
Quad Speed Mode (DFS0=“0”, DFS1=“1”)
fsq
176.4
Duty Cycle
Slave mode
45
Master mode
50
Audio Interface Timing
Slave mode
BICK Period
tBCK
81
BICK Pulse Width Low
tBCKL
33
Pulse Width High
tBCKH
33
LRCK Edge to BICK “↑”
(Note 16)
tLRB
20
BICK “↑” to LRCK Edge (Note 16)
tBLR
20
LRCK to SDTO (MSB) (Except I²S mode)
tLRS
BICK “↓” to SDTO
tBSD
SDTI Hold Time
tSDH
20
SDTI Setup Time
tSDS
20
Master mode
BICK Frequency
fBCK
64fs
BICK Duty
BICK “↓” to LRCK
BICK “↓” to SDTO
dBCK
50
tMBLR
−20
tBSD
−20
SDTI Hold Time
tSDH
20
SDTI Setup Time
tSDS
20
Note: 15. Duty cycle is not guaranteed when using the external clock input.
Note: 16. BICK rising edge must not occur at the same time as LRCK edge.
[AK4584]
max
24.576
36.864
24.576
60
18.432
60
192
48
96
192
55
Units
MHz
MHz
ns
ns
MHz
%
MHz
%
kHz
kHz
kHz
kHz
%
%
ns
ns
ns
ns
ns
20
ns
20
ns
ns
ns
Hz
%
20
ns
20
ns
ns
ns
MS0118-E-00
- 12 -
2001/11