AK4584_01 Datasheet, PDF (40/53 Pages) Asahi Kasei Microsystems – 24Bit 96kHz Audio CODEC with DIT/DIR

ASAHI KASEI
[AK4584]
Addr
04H
05H
Register Name
Lch IPGA Control
Rch IPGA Control
R/W
Default
D7
IPGL7
IPGR7
R/W
0
D6
IPGL6
IPGR6
R/W
1
D5
IPGL5
IPGR5
R/W
1
D4
IPGL4
IPGR4
R/W
1
D3
IPGL3
IPGR3
R/W
1
D2
IPGL2
IPGR2
R/W
1
D1
IPGL1
IPGR1
R/W
1
D0
IPGL0
IPGR0
R/W
1
IPGL/R7-0: ADC Input Gain Level (see Table 23)
Initial value is “7FH” (0dB).
Digital ATT with 128 levels operates when writing data of less than 7FH. This ATT is a linear ATT with 8032
levels internally and these levels are assigned to pseudo-log data with 128 levels. The transition between ATT
values has 8032 levels and is done by soft changes. For example, when ATT changes from 127 to 126, the
internal ATT value decreases from 8031 to 7775, one by one every fs cycle. It takes 8031 cycles
(182ms@fs=44.1kHz) from 127 to 0 (Mute).
The IPGAs are set to “00H” when PDN pin goes “L”. After returning to “H”, the IPGAs fade into the initial
value, “7FH” in 8031 cycles.
The IPGAs are set to “00H” when PWADN bit goes “0”. After returning to “1”, the IPGAs fade into the current
value. The ADC output is “0” during the first 516 cycles.
The IPGAs are set to “00H” when RSTADN bit goes to “0”. After returning to “1”, the IPGAs fade into the
current value. The ADC output is “0” during the first 516 cycles.
MS0118-E-00
- 40 -
2001/11