AK4584_01 Datasheet, PDF (34/53 Pages) Asahi Kasei Microsystems – 24Bit 96kHz Audio CODEC with DIT/DIR

ASAHI KASEI
[AK4584]
„ Soft Mute Operation
Soft mute operation is performed in the digital domain of the DAC input. When the SMUTE bit goes to “1”, the output
signal is attenuated by −∞ during 1024 LRCK cycles. When the SMUTE bit is returned to “0”, the mute is cancelled and
the output attenuation gradually changes to 0dB during 1024 LRCK cycles. If the soft mute is cancelled within 1024 LRCK
cycles after starting the operation, the attenuation is discontinued and returned to 0dB. The soft mute is effective for
changing the signal source without stopping the signal transmission.
Soft mute function is independent of the output volume and cascade connected between both functions.
SMUTE
0dB
Attenuation
1024/fs
(1)
1024/fs
(3)
-∞
LOUT / ROUT
GD
GD
(2)
DZF pin
(4)
8192/fs
Figure 16. Soft mute function and Zero detection function
(1) The output signal is attenuated by −∞ during 1024 LRCK cycles (1024/fs).
(2) Analog output delay from the digital input is called the group delay (GD).
(3) If the soft mute is cancelled within 1024 LRCK cycles, the attenuation is discontinued and returned to 0dB.
(4) When the input data of both channels is continuously zeros for 8192 LRCK cycles, DZF pin goes to “H”. DZF pin
immediately goes to “L” if input data of any channel is not zero after going DZF pin = “H”.
„ Zero Detection Function
The AK4584 DAC has a L/R channel-dependent zeros detect function. When the input data at both channels is
continuously zero for 8192 LRCK cycles, the DZF pin of each channel goes to “H”. The DZF pin of each channel
immediately goes to “L” if the input data of each channel is not zero after DZF pin = “H”. Zero detect function can be
disabled by the DZFE bit. In this case, the DZF pin is always “L”.
When the PDN pin is “L”, the DZF pin is always “L”. If PDN pin = “L” → “H”, DZF pin goes from “L” → “H”. When the
PWVRN bit is “0”, the DZF pin is “L”.
If the DZF pin goes to “H” when the RSTDAN bit becomes “0”, then the AK4584 is reset after 4~5/fs and goes to “L” at
6~7/fs after the RSTDAN bit becomes “1”. If after the RSTDAN bit becomes “0” and within 5/fs, the RSTDAN bit
becomes “1”, then the AK4584 will not be properly reset.
If the DZF pin goes to “H” when the PWDAN bit becomes “0”, then the AK4584 is reset after 4~5/fs and goes to “L” at
6~7/fs after the PWDAN bit becomes “1”. If the PWDAN bit becomes “0”, and the PWDAN bit becomes “1” within 5/fs,
then the AK4584 will not be properly reset.
When PDN pin becomes “H” and the PWDAN bit becomes “1” and the RSTDAN bit becomes “1”, 8192 counts start after
1/fs for the zero detect function.
MS0118-E-00
- 34 -
2001/11