AK4584_01 Datasheet, PDF (19/53 Pages) Asahi Kasei Microsystems – 24Bit 96kHz Audio CODEC with DIT/DIR

ASAHI KASEI
[AK4584]
OPERATION OVERVIEW
„ Internal Signal Path
The input source of the DAC and SDTO can be switched between the outputs of the ADC, SDTI or the DIR. The input
source of the DIT can be switched between the outputs of ADC or SDTI. There is also a through/bypass path from the DIR
to the DIT that can be also selected. The Switch Names (DAC1-0 etc) in Figure 1 correspond to the register bits that control
the switch function. Refer to “Register Definitions” (Address 08H).
IPGA
ADC
HPF
DATT
DAC1-0
DEM ^DATT DAC
SMUTE
SDTI
PCM1-0
SDTO
DIR
DIT1-0
DIT
DIT1-0
Figure 1. Connection between Input Sources & Output Sources
„ Clock Operation Mode
The CM1-0 bits determine the clock source of the AK4584; either PLL or X’tal (including external clock source, Table 1).
In mode 2, the clock source is switched automatically from PLL to X’tal when the PLL loses lock. In mode 3, the clock
source is fixed to the external X’tal input, however the PLL is also operating enabling the monitoring of recovered data
such as C bits. For mode 2 and mode 3, the frequency of the X’tal should be different from that of the recovered frequency
from PLL. When XTL1-0 bits are “11”, the X’tal oscillator is stopped in mode 0. The default values are “01” for CM1-0
bits.
Since the signal path is not changed automatically when changing the CM1-0 bits, the output source should be selected by
changing register 08H.
Mode
0
1
2
3
CM1
CM0 UNLOCK PLL X’tal Clock Source
0
0
-
ON
∗
PLL
0
1
-
OFF ON
X’tal
1
0
0
ON ON
PLL
1
ON ON
X’tal
1
1
-
ON ON
X’tal
ON: Oscillation (Power-up), OFF: STOP (Power-down)
∗ : OFF at XTALE pin = “L” and XTL1-0 bits = “11”, ON at others
Table 1. Clock Operation Mode Select
Default
MS0118-E-00
- 19 -
2001/11