AK7714 Datasheet, PDF (39/48 Pages) Asahi Kasei Microsystems – 20-Bit Audio Codec with DSP and Delay RAM

[ASAHI KASEI]
[AK7714]
b) External conditional jump code rewrite (during RUN phase)
Data comprising a set of two bytes is used to write the external conditional jump code. Data can be input during both
the reset and operation phases, and input data is set to the specified register at the rising edge of LRCLK. When all
data has been transferred, the RDY terminal goes to "L". Upon completion of writing, it goes to "H". A jump command
will be executed if there is any one agreement between each bit of the 8-bit external condition code and "1"of each bit of
the IFCON field. A write operation from the microcomputer is disabled until RDY goes to "H".
Note: The LRCLK phase is inverted in the I2S-compatible state.
Data transfer procedure
{¹ Command code
{² Code .data
(11000100)
(D7......D0)
External condition jump write timing (during RUN phase)
M0018-E-00
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‘98/07