AK7714 Datasheet, PDF (22/48 Pages) Asahi Kasei Microsystems – 20-Bit Audio Codec with DSP and Delay RAM

[ASAHI KASEI]
[AK7714]
5) Control registers
The control registers (16 bits) can be set via the microcomputer interface in addition to the control pins.
For the value to be written in the control registers, see the description of the microcomputer interface.
The following describes the control register map.
Control register map (
indicates the default values.)
Code
Function
C15 Selects the data reset function after reset is released. 0: Used
1: Unused
C14 Selects delay RAM sampling
0: 1Sampling
1: 2 Sampling
C13 Selects DRAM addressing method
0: Ring addressing
1: Linear addressing
C12 Random number generator circuit
0: Unused
1: Used
C11 Test mode (Use at 0)
0: Normal operation
1: Test mode
C10 Test mode (Use at 0)
0: Normal operation
1: Test mode
C9 Test mode (Use at 0)
0: Normal operation
1: Test mode
C8 Resets ADC section
0: Normal operation
1: Reset
C7 Sets internal path
0: ADC serial data selected 1: SDIN1 selected
C6 Sets internal path
0: Normal setting
1: Sets the path selected by C7
C5 DAC2 section reset control
0: Normal operation
1: DAC2 section reset
C4 DAC1 section reset control
0: Normal operation
1: DAC1 section reset
C3 SDOUT output enable
0: SDOUT = Output
1: SDOUT = "L"
C2 Selects SDIN1 and SDIN2 input mode.
C1
Mode C2
C1
1
0
0 MSB first (24 bits)
2
0
1 LSB first (24 bits)
3
1
0 LSB first (20 bits)
4
1
1 LSB first (16 bit)
Note: When CØ = 1, the state is I²S compatible independent of mode setting; however, set to Mode 1.
C0 Select I²S compatible.
0: Normal setting
1: I²S compatible (In this case, all input/output pins are I²S compatible.)
Data can be loaded into the control registers only when DSP RESET = "L" and CODEC RESET = "L". If used
otherwise, an operation error will occur. To avoid an operation error, do not use it.
M0018-E-00
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‘98/07