AK7714 Datasheet, PDF (34/48 Pages) Asahi Kasei Microsystems – 20-Bit Audio Codec with DSP and Delay RAM

[ASAHI KASEI]
[AK7714]
e) External conditional jump code write (during reset phase)
Data comprising a set of two bytes is used to perform the external conditional jump code write operation. The data can
be input during both the reset and operation phases, and the input data is set to the specified register at the leading
edge of LRCLK. When all data has been transferred, the RDY terminal goes to "L". Upon completion of writing, it goes
to "H". A jump command will be executed if there is any one agreement between "1" of each bit of the external condition
code 8 bits (soft set) plus 1 bit (hard set) at the external input terminal JX and "1" of each bit of the IFCON field. The
data during the reset phase can be written only before release of the reset, after all data has been transferred. WRQ
transition from "L" to "H" in the write operation during the reset phase must be executed after three LRCLK in the slave
mode and one LRCLK in master mode, respectively, from the falling edge of LRCLK after release of the reset. Then
RDY goes to "H" after capturing the rise of the next LRCLK. Write operation from the microcomputer is disabled until
RDY goes to "H". The IFCON field provides external conditions written on the program.
Note: The LRCLK phase is inverted in the I2S-compatible state.
7
0JX
External condition code „ „ „ „ „ „ „ „ †
↑
Check if there is any one agreement between the bit specified
in IFCON and "1" in the external condition code.
16
↓
8
IFCON field
‹‹‹‹‹‹‹‹‹
Data transfer procedure
{¹ Command code (11000100)
{² Code data
(D7......D0)
Timing for external conditional jump write operation (during reset phase)
M0018-E-00
- 34 -
‘98/07