AK7714 Datasheet, PDF (21/48 Pages) Asahi Kasei Microsystems – 20-Bit Audio Codec with DSP and Delay RAM

[ASAHI KASEI]
[AK7714]
Function Description
(1) Various settings
1) OPCL (pin 34): ADC and DAC connection selector pin (See Block Diagram on page 2.)
† Normally, OPCL is used in "L" or open. (Internal connection mode)
In this case, ADC output and DAC1/DAC2 inputs are directly connected to the DSP internally. At this time, leave the
SDINA (pin 12), SDIND1 (pin 17) and SDIND2 (pin 18) open or set to "L".
It should be noted that "L" is output from the SDOUTA (pin 14), SDOUTD1 (pin 15) and SDOUTD2 (pin 20).
† When the OPCL is set to "H", the ADC output and DAC1/DAC2 inputs can be used independently from the DSP.
(Input/output formats are restricted.)
Note: SDINA supports only MSB-first 24-bit input (including I²S compatibility).
SDOUTA supports only MSB-first 20-bit output (including I²S compatibility).
SDIND1 and SDIND2 support only MSB-first 20-bit inputs (including I²S compatibility).
2) CTRL1 (pin 62) and CTRL0 (pin 56): clock output control pins
CLKO output and LRCLK and BITCLK outputs in the master mode can be fixed to "L" or "H"
by setting these two pins.
Mode
1
2
3
4
CTRL1
0
0
1
1
CTRL0
0
1
0
1
Master mode
Master mode
CLKO
LRCLK
BITCLK
Output
Output
Output
Disabled (This is a test mode, so do not use it.)
"L"
Output
Output
"L"
"H" (For "L", see Note.)
"L"
Note: When CTRL1 and CTRL0 are used in the open state, Mode 1 will be selected.
Output is set to "L" when I²S compatible.
Mode 4 can be used only when the AK7714 is used "Analog to Analog".
3) CKS1 (pin 64) and CKS0 (pin 63): Clock selector pin
CKS1
0
0
1
1
CKS0
0
1
0
1
XTI
DSP
384fs
384fs
512fs
512fs
256fs
256fs
Test mode (disabled)
fs: Sampling frequency
4) SMODE (pin 65): Slave and master mode selector pin
Sets LRCLK (pin 36) and BITCLK (pin 37) to either input or output.
a) Slave mode: SMODE = "L"
LRCLK (1 fs) and BITCLK (48 fs or 64 fs) become input.
b) Master mode: SMODE = "H"
LRCLK (1 fs) and BITCLK (64 fs) become output.
M0018-E-00
- 21 -
‘98/07