AK7714 Datasheet, PDF (25/48 Pages) Asahi Kasei Microsystems – 20-Bit Audio Codec with DSP and Delay RAM

[ASAHI KASEI]
[AK7714]
(3) Resetting
The AK7714 has three reset pins: INIT RESET,DSP RESET and CODEC RESET.
The INIT RESET pin is used to initialize the AK7714, as shown in "Power supply startup sequence above."
DSP RESET and CODEC RESET are normally controlled simultaneously. The system is reset when
DSP RESET = "L" and CODEC RESET = "L". (Description of "reset" is for "system reset".)
Under the condition of this system reset, the program write operation is performed (except for write operation during
running).
During the system reset phase, the ADC and DAC sections are also reset. (The digital section of ADC output is MSB
first 00000h and the analog section of DAC output is Hi-z. )
CLKO is output even during the system reset phase if CTRL (1:0) = 0h (Mode 1), but LRCLK and BITCLK in the master
mode will stop.
The system reset is released by setting either DSP RESET or CODEC RESET to "H", and this will activate the internal
counter. LRCLK and BITCLK in the master mode are generated by this counter: however, a hazard may occur when a
clock signal is generated. When the system reset is released in the slave mode, internal timing will be actuated in
synchronization with "↑" of LRCLK (when the standard input format is used). Timing between the external and internal
clocks is adjusted at this time. If the phase difference in LRCLK and internal timing is within about -1/16 to 1/16 of the
input sampling cycle (1/fs) during the operation, the operation is performed with internal timing remaining unchanged. If
the phase difference exceeds the above range, the phase is adjusted by synchronization with "↑" of LRCLK (when the
standard input format is used). This is a circuit to prevent failure of synchronization with the external circuit owing to
noise and the like. For some time after returning to the normal state after loss of synchronization, normal data will not
be output. If you want to change the clock, do so while the system is reset.
The ADC section can output 516-LRCLK after its internal counter started. (The internal counter starts at the first rising
edge of LRCLK at master mode. In case of slave mode, it starts end of 2LRCLK after release of system reset. )
The AK7714 performs normal operation when both DSP RESET and CODEC RESET are set to "H".
(4) System clock
The required system clock is XTI (256 fs/384 fs/512 fs), LRCLK (fs) and BITCLK (64 fs) in the slave mode, and is XTI
(256 fs/384 fs/512 fs) in the master mode.
LRCLK corresponds to the standard digital audio rate (32 kHz, 44.1 kHz, 48 kHz).
fs
XTI
(Master clock)
BITCLK
256 fs
384 fs
512 fs
64 fs
32.0 kHz
- Note
12.2880 MHz 16.3840 MHz
2.0480 MHz
44.1 kHz
11.2896 MHz 16.9344 MHz 22.5792 MHz
2.8224 MHz
48.0 kHz
12.2880 MHz 18.4320 MHz
- Note
3.0720 MHz
Note: 256 fs is not supported at fs = 32.0 kHz. 512fs is not supported at fs = 48.0 kHz.
SMODE
L
L
L
H
H
H
CKS1
L
L
H
L
L
H
CKS0
L
H
L
L
H
L
XTI
384 fs
512 fs
256 fs
384 fs
512 fs
256 fs
LRCLK, BITCLK
Input
Input
Input
Output
Output
Output
M0018-E-00
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‘98/07