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AK4495SEQ Datasheet, PDF (17/58 Pages) Asahi Kasei Microsystems – Quality-oriented Premium 32-Bit 2ch DAC | |||
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[AK4495S]
Control Interface Timing
CCLK Period
tCCK
200
ns
CCLK Pulse Width Low
tCCKL
80
ns
Pulse Width High
tCCKH
80
ns
CDTI Setup Time
tCDS
50
ns
CDTI Hold Time
tCDH
50
ns
CSN High Time
tCSW
150
ns
CSN âï¯â to CCLK âïâ
tCSS
50
ns
CCLK âïâ to CSN âïâ
tCSH
50
Control Interface Timing (I2C Bus mode):
SCL Clock Frequency
fSCL
-
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time (prior to first clock pulse) tHD:STA 0.6
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA 0.6
SDA Hold Time from SCL Falling
(Note 20) tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT 0.1
Rise Time of Both SDA and SCL Lines
tR
-
Fall Time of Both SDA and SCL Lines
tF
-
Setup Time for Stop Condition
tSU:STO 0.6
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
0
ns
400 kHz
-
ïs
-
ïs
-
ïs
-
ïs
-
ïs
-
ïs
-
ïs
0.3 ïs
0.3 ïs
-
ïs
50
ns
Capacitive load on bus
Cb
-
400 pF
Reset Timing
PDN Pulse Width
(Note 21)
tPD
150
ns
Note 17. 1152fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs ãåãæ¿ããå ´åã¯PDN pinã¾ãã¯RSTN bitã§
ãªã»ãããã¦ä¸ããã
Note 18. ãã®è¦æ ¼å¤ã¯LRCKã®ã¨ãã¸ã¨BICKã®âïâãéãªããªãããã«è¦å®ãã¦ãã¾ãã
Note 19. ãã¼ã¿éä¿¡å´ã«è¦æ±ãããå¤ã§ãã
Note 20. ãã¼ã¿ã¯æä½300ns(SCLã®ç«ã¡ä¸ããæé)ã®éä¿æãããªããã°ãªãã¾ããã
Note 21. é»æºæå
¥æã¯PDN pinãâLâããâHâã«ãããã¨ã§ãªã»ããããããã¾ãã
MS1560-J-01
- 17 -
2013/11
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