HMC702LP6CE Datasheet, PDF (31/38 Pages) Hittite Microwave Corporation – 14 GHz 16-Bit Fractional-N Synthesizer

v10.0812
HMC702LP6CE
14 GHz 16-BIT FRACTIONAL-N PLL

Table 21. Reg 0Fh Integer Division Register
Bit
Type
Name
Default
15:0
R/W dsm_intg
C8h
Description
unsigned integer portion of VCO divider value,
also known as N_INT, see ( EQ 12)
Table 22. Reg 10h Fractional Division Register
Bit
Type
Name
Default
23:0
R/W dsm_frac
0
Description
unsigned fractional portion of VCO divider also
known as N_FRAC, see (EQ 12)
Table 23. Reg 11h Seed Register
Bit
Type
Name
23:0
R/W dsm_seed
Default
0
Description
Unsigned seed value for Δ∑ modulator
Sets the start phase of the modulator. Use a
random , non-repeating number for best results
(examples: 3A1953h, DEADBEh, 50894Ch)
Table 24. Reg 12h Delta Sigma Modulator Register
Bit
Type
Name
Default
Description
0
R/W dsm_ref_clk_select
0
use reference instead of divider Program 0
1
R/W dsm_invert_clk_sd3
1
invert Δ∑ clk
2
R/W dsm_invert_clk_rph
0
inverts the ref clock phase
3
R/W dsm_integer_mode
1- enables Integer Mode, bypasses the Δ∑
0
modulator, leaves it running
see also dsm_rstb Reg01h<13> to disable the
modulator
4
R/W Reserved
0
5
R/W Reserved
0
6
R/W dsm_xref_sin_select
7
R/W dsm_autoseed
9:8
R/W dsm_order
13:10
17:14
R/W dsm_quant_max
R/W dsm_quant_min
0
when xref is selected specifies that the sine
source is used
1
automatic seed load when changing the frac
part, uses value in seed
Delta-Sigma Modulator configuration:
00-1st order 01-2nd order 10-3rd order Feedback
2h
11-3rd order Feedforward
Use either 10 or 11. For Sweeper operation use
11 only.
Do not use 1st or 2nd order (for test only)
3h
max value allowed out of Δ∑ modulator quantizer
limits are +7 to -8, typ ±3 or ±4 Program 3h
Ch
min value allowed out of Δ∑ modulator quantizer
limits are +7 to -8, typ ±3 or ±4 Program Ch
[1] Phase-Error Measurement and Compensation in PLL Frequency Synthesizers for FMCW, Sensors—I: Context and Application, Pichler, Stelzer,
Member, IEEE, Seisenberger, and Vossiek, IEEE Transactions on Circuits and Systems—I, VOL. 54, No. 5, May 2007
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