HMC702LP6CE Datasheet, PDF (26/38 Pages) Hittite Microwave Corporation – 14 GHz 16-Bit Fractional-N Synthesizer

v10.0812
HMC702LP6CE
14 GHz 16-BIT FRACTIONAL-N PLL

LD status always:
Reg2h[1:0] = 11
Reg1Ah[13:12] = 01
High impedance always:
Reg2h[1:0] = 10
Reg1Ah[13:12] = xx (x=don’t care)
Serial Port WRITE Operation
AVDD = DVDD = 3V ±10%, AGND = DGND = 0V
Table 4. Timing Characteristics
Parameter
Conditions
t₁
SEN to SCLK setup time
t₂
SDI to SCLK setup time
t₃
SDI to CLK hold time
t₄
SCLK high duration
t₅
SCLK low duration
t₆
SEN High duration
t₇
SEN low duration
Min.
8
10
10
8
8
640
20
Typ.
Max
Units
nsec
nsec
nsec
nsec
nsec
nsec
nsec
A typical WRITE cycle is shown in Figure 19.
a. The Master (host) both asserts SEN (Serial Port Enable) and clears SDI to indicate a WRITE
cycle, followed by a rising edge of SCLK.
b. The slave (synthesizer) reads SDI on the 1st rising edge of SCLK after SEN. SDI low initiates
the WRITE cycle (/WR)
c. Host places the six address bits on the next six falling edges of SCLK, MSB first.
d. Slave registers the address bits in the next six rising edges of SCLK (2-7).
e. Host places the 24 data bits on the next 24 falling edges of SCK, MSB first .
f. Slave registers the data bits on the next 24 rising edges of SCK (8-31).
g. SEN is de-asserted on or after the 32nd falling edge of SCLK.
h. The 32^nd rising edge of SCLK completes the cycle
Figure 19. Serial Port Timing Diagram - WRITE
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