HMC702LP6CE Datasheet, PDF (2/38 Pages) Hittite Microwave Corporation – 14 GHz 16-Bit Fractional-N Synthesizer

v10.0812
HMC702LP6CE
14 GHz 16-BIT FRACTIONAL-N PLL

General Description
The HMC702LP6CE is a SiGe BiCMOS fractional-N PLL. The fractional-N PLL includes a fixed divide by 2 followed by
a 8GHz 16-bit RF N-Divider, a 24-bit delta-sigma modulator, a very low noise digital phase frequency detector (PFD),
and a precision controlled charge pump.
The fractional-N PLL features an advanced delta-sigma modulator design that allows ultra-fine frequency step sizes.
The fractional-N PLL features the ability to alter both the phase-frequency detector (PFD) gain and the cycle slipping
characteristics of the PFD. This feature can reduce the time to arrive at the new frequency by 50% vs. conventional
PFDs. Ultra low in-close phase noise also allows wider loop bandwidths for faster frequency hopping.
The fractional-N PLL contains a built-in linear sweeper function, which allows it to perform frequency chirps with a
wide variety of sweep times, polarities and dwells, all with an external or automatic sweep trigger.
In addition the fractional-N PLL has a number of auxiliary clock generation modes that can be accessed via the GPO.
Electrical Specifications, T_A = +25°C
VCCHF = VCCPRS = RVDD = +3.3V
VPPCP = VCCOA = VDDPDR = VPPDRV = VDDPD = VDDPDV = +5V
DVDD = DVDDIO = DVDDQ = +3.3V
GNDDRV = GNDCP = GNDPD = GNDPDV = GNDPDR = 0V
Table 1. Electrical Specifications
Parameter
Prescaler Characteristics
Max RF Input Frequency (3.3V)
Max RF Input Frequency (2.7 - 3.3V)
Min RF Input Frequency
RF Input Power
16-bit N-Divider Range (Integer)
16-bit N-Divider Range (Fractional)
REF Input Characteristics
Max Ref Input Frequency (pin XREFP)
Max Ref Input Frequency (pin XSIN)
Min Ref Input Frequency
Ref Input Voltage Range (pin XREFP)
Ref Input Power Range (pin XSIN)
Ref Input Capacitance
14-Bit R-Divider Range
Conditions / Notes
Min
Typ
12
14
12
13
0.1
Fmin<Fvco<10 GHz
Fvco>10 GHz
-10
-6
0
16-Bit divider and fixed divide-by-2
step of 2
64
Fraction Nominal Divide ratio varies
(-6 / +8) dynamically max
72
250
250
XSIN minimum 20MHz due to
phase noise degradation
100
AC Coupled
1.5
2.0
50 Ω Source
-6
0
1
Max
Units
10
131,070
131,062
GHz
GHz
MHz
dBm
3.3
12
5
16,383
MHz
MHz
kHz
Vpp
dBm
pF
Irne_Ffsop_orom_{rnastpiiborinliitcyfueirsn,aisshdseue}dm_{lebivdy ebAyr}n_yAalnoaaglonDg_deDvei_tcv_oeicse_psislfaobrceitli_esevuesode_{r, d}tnoo_{erbrfeosra:acnH}cyui_irn_taf_trteiintgeaenmd_Merneitclsia_roboflepw.atHe_aon_vwts_eeovre_Cor,thoneo_rrp
rliicgehntsseofisthgirrdanptaerdtiebsythimatpmlic_Paay_htioroens_nuolr_et _of:rtohm_{9er7wits8isue-}s₂eu.n_5dS0epre-ca₃infi_3ycap4tiao_{3tnesntsourbF}jpea_actte_xtno_:t cr₉higa_7hnt8gse_-o2wf _Ai5thn₀oaulo_-tg₃noD₃tiec_7vei3.ceNso.
o^FOr^oa_nrt_ei^po_Tren^icc,^eh2^,nodE_leol^lgi^ivz_yea^rWb^y,ae_yat_,nh_Pd.D_Oto.ri_Bv^poe^lax,^c9eC₁₀h^o6re^d,l^eNm^ross^:rwf^Ao_onr_oad_dl,^{o, gM}M_ADA^e0v0_2ic01^e68^s22^,-94^In10c.6,
O_Pr_hd_one_er_: O₇₈n₁-_-3li₂n₉e_-4a₇t₀₀w_•w_Ow_rd._eh_rit_ot_nit_le_in._ec_ao_tm_{www.analog.com}
2
Trademarks and registered trademarks a_Are_pth_pe_lp_ir_cop_ae_tr_ity_oo_nf th_Sei_ur r_pes_ppe_oct_riv_te_: o_Pw_hne_ors_n. _{e: 978-250-33}A₄p₃plic_oa_rtio_an_pS_pu_sp_@po_hrt_i:_tP_tih_teo_.n_ce_o: 1_m-800-ANALOG-D