HMC702LP6CE Datasheet, PDF (18/38 Pages) Hittite Microwave Corporation – 14 GHz 16-Bit Fractional-N Synthesizer

v10.0812
HMC702LP6CE
14 GHz 16-BIT FRACTIONAL-N PLL

Figure 13. Delayed Lock Detect Window
For most applications the analog one shot window is sufficient. To determine the required Lock Detect one shot
window size:
Required LD One Shot Window = (CP Phase Offset (ns) + 8xTvco) x 1.3.
Cycle Slip Prevention (CSP)
When changing frequencies the VCO is not yet locked to the reference and the phase difference at the PFD varies
rapidly over a range much greater than ±2π radians. Since the gain of the PFD varies linearly with phase up to ±2π,
the gain of conventional PFDs will cycle from high gain, when the phase difference approaches a multiple of 2π, to
low gain, when the phase difference is slightly larger than a multiple of 0 radians. This phenomena is known as cycle
slipping. Cycle slipping causes the pull-in rate during the locking phase to vary cyclically as shown in the red curve in
Figure 14. Cycle slipping increases the time to lock to a value far greater than that predicted by normal small signal
Laplace analysis.
The HMC702LP6CE PFD features Cycle Slip Prevention (CSP), an ability to virtually eliminate cycle slipping during
acquisition. When enabled, the CSP feature essentially holds the PFD gain at maximum until such time as the frequency
difference is near zero. CSP allows significantly faster lock times as shown inFigure 14. The use of the CSP feature is
enabled with pfds_rstb (Reg01<15> Table 7). The CSP feature may be optimized for a given set of PLL dynamics by
adjusting the PFD sensitivity to cycle slipping. This is achieved by adjusting pfds_sat_deltaN (Reg1C<3:0> Table 33).
CSP will cause the VCO N divider to momentarily divide by a higher or lower N value in order to pull the divided VCO
phase back towards the reference edge. The maximum recommended VCO N divider deviation is no more than
20% of the target N value programmed into Register F. For example, if N=50 for the target frequency, then the CSP
Magnitude should be 10 or less so Register 1Ch Bits [3:0] would be programmed to Ah.
In situations where the target N value is low, for example 36 the CSP behavior will be compromised because the
minimum VCO divide value is 32.
Figure 14. Cycle Slip Prevention (CSP)
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