82-000770-01 Datasheet, PDF (31/91 Pages) Analog Devices – ADSP-TS201S EZ-KIT Lite Evaluation System

Using ADSP-TS201S EZ-KIT Lite
For the supplied memory, the SDRCON register should be configured as
follows:
• SDRAM enable, CAS latency of two cycles
• Pipe depth of zero, page boundary of 256 words
• Refresh rate of every 3700 cycles, precharge to RAS of two cycles
• RAS to precharge of five cycles
• Init sequence is MRS cycle follows refresh
[ The SYSCON and SDRCON registers define bus control configuration.
They can be written only once after reset and cannot be changed
during system operation.
L In emulation space, the SYSCON and the SDRCON registers can be
written to as many times as needed. The USB debug monitor oper-
ates in emulation space and allows “always writable” mode for these
registers.
Flash Memory
The AT49BV040 chip provides a total of 512K x 8-bits of external flash
memory, arranged into eight uniform 64 Kb memory blocks. The block
addresses are shown in Table 1-2.
Table 1-2. Flash Memory Map
Start Address
0x3000 0000
0x3001 0000
0x3002 0000
0x3003 0000
End Address
0x3000 FFFF
0x3001 FFFF
0x3002 FFFF
0x3003 FFFF
Content
Uniform block 0
Uniform block 1
Uniform block 2
Uniform block 3
ADSP-TS201S EZ-KIT Lite Evaluation System Manual
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