Z8F042ASJ020EG2156 Datasheet, PDF (95/280 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F082A Series
Product Specification
79
If TPOL is set to 1, the ratio of the PWM output High time to the total period is repre-
sented by:
PWM Output High Time Ratio (%) = --^P----^W-----^M------^V----^a---^l-^u---^e----  100
Reload Value
Capture Mode
In Capture Mode, the current timer count value is recorded when the appropriate external
Timer Input transition occurs. The Capture count value is written to the Timer PWM High
and Low Byte registers. The timer input is the system clock. The TPOL bit in the Timer
Control Register determines if the Capture occurs on a rising edge or a falling edge of the
Timer Input signal. When the Capture event occurs, an interrupt is generated and the timer
continues counting. The INPCAP bit in TxCTL0 Register is set to indicate the timer inter-
rupt is because of an input capture event.
The timer continues counting up to the 16-bit reload value stored in the Timer Reload
High and Low Byte registers. Upon reaching the reload value, the timer generates an inter-
rupt and continues counting. The INPCAP bit in TxCTL0 Register clears indicating the
timer interrupt is not because of an input capture event.
Observe the following steps for configuring a timer for Capture Mode and initiating the
count:
1. Write to the Timer Control Register to:
– Disable the timer
– Configure the timer for Capture Mode
– Set the prescale value
– Set the Capture edge (rising or falling) for the Timer Input
2. Write to the Timer High and Low Byte registers to set the starting count value (typi-
cally 0001h).
3. Write to the Timer Reload High and Low Byte registers to set the reload value.
4. Clear the Timer PWM High and Low Byte registers to 0000h. Clearing these registers
allows the software to determine if interrupts were generated by either a capture event
or a reload. If the PWM High and Low Byte registers still contain 0000h after the
interrupt, the interrupt was generated by a Reload.
5. Enable the timer interrupt, if appropriate and set the timer interrupt priority by writing
to the relevant interrupt registers. By default, the timer interrupt is generated for both
input capture and reload events. If appropriate, configure the timer interrupt to be gen-
erated only at the input capture event or the reload event by setting TICONFIG field
of the TxCTL0 Register.
PS022828-0413
PRELIMINARY
Operation