Z8F042ASJ020EG2156 Datasheet, PDF (76/280 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F082A Series
Product Specification
60
Caution: To avoid retriggerings of the Watchdog Timer interrupt after exiting the associated inter-
rupt service routine, Zilog recommends that the service routine continues to read from
the RSTSTAT Register until the WDT bit is cleared as shown in the following example.
CLEARWDT:
LDX r0, RSTSTAT ; read reset status register to clear wdt bit
BTJNZ 5, r0, CLEARWDT ; loop until bit is cleared
Interrupt Control Register Definitions
For all interrupts other than the Watchdog Timer interrupt, the Primary Oscillator Fail
Trap and the Watchdog Oscillator Fail Trap, the interrupt control registers enable individ-
ual interrupts, set interrupt priorities and indicate interrupt requests.
Interrupt Request 0 Register
The Interrupt Request 0 (IRQ0) Register, shown in Table 35, stores the interrupt requests
for both vectored and polled interrupts. When a request is presented to the interrupt con-
troller, the corresponding bit in the IRQ0 Register becomes 1. If interrupts are globally
enabled (vectored interrupts), the interrupt controller passes an interrupt request to the eZ8
CPU. If interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the
Interrupt Request 0 Register to determine if any interrupt requests are pending.
Table 35. Interrupt Request 0 Register (IRQ0)
Bit
7
6
Field
Reserved T1I
RESET
0
0
R/W
R/W
R/W
Address
5
4
3
2
1
0
T0I
U0RXI U0TXI Reserved Reserved ADCI
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
FC0H
Bit
Description
[7]
Reserved
This bit is reserved and must be programmed to 0.
[6]
Timer 1 Interrupt Request
T1I
0 = No interrupt request is pending for Timer 1.
1 = An interrupt request from Timer 1 is awaiting service.
[5]
Timer 0 Interrupt Request
T0I
0 = No interrupt request is pending for Timer 0.
1 = An interrupt request from Timer 0 is awaiting service.
PS022828-0413
PRELIMINARY
Interrupt Control Register Definitions