Z8F042ASJ020EG2156 Datasheet, PDF (101/280 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F082A Series
Product Specification
85
Time 0–1 Control Register 0
The Timer Control Register 0 (TxCTL0) and Timer Control Register 1 (TxCTL1), shown
in Table 50, determine the timer operating mode. These registers each include a program-
mable PWM deadband delay, two bits to configure timer interrupt definition and a status
bit to identify if the most recent timer interrupt is caused by an input capture event.
Table 50. Timer 0–1 Control Register 0 (TxCTL0)
Bit
7
Field
TMODEHI
RESET
0
R/W
R/W
Address
6
5
TICONFIG
0
0
R/W
R/W
4
3
Reserved
0
0
R/W
R/W
F06H, F0EH
2
PWMD
0
R/W
1
0
INPCAP
0
0
R/W
R
Bit
[7]
TMODEHI
[6:5]
TICONFIG
[4]
[3:1]
PWMD
[0]
INPCAP
Description
Timer Mode High Bit
This bit, along with the TMODE field in the TxCTL1 Register, determines the operating
mode of the timer. This bit is the most significant bit of the timer mode selection value. See
the description of the Timer 0–1 Control Register 1 (TxCTL1) for details about the full timer
mode decoding.
Timer Interrupt Configuration
This field configures timer interrupt definition.
0x = Timer Interrupt occurs on all defined Reload, Compare and Input Events.
10 = Timer Interrupt only on defined Input Capture/Deassertion Events.
11 = Timer Interrupt only on defined Reload/Compare Events.
Reserved
This bit is reserved and must be programmed to 0.
PWM Delay Value
This field is a programmable delay to control the number of system clock cycles delay
before the Timer Output and the Timer Output Complement are forced to their active state.
000 = No delay.
001 = 2 cycles delay.
010 = 4 cycles delay.
011 = 8 cycles delay.
100 = 16 cycles delay.
101 = 32 cycles delay.
110 = 64 cycles delay.
111 = 128 cycles delay.
Input Capture Event
This bit indicates if the most recent timer interrupt is caused by a Timer Input Capture Event.
0 = Previous timer interrupt is not a result of Timer Input Capture Event.
1 = Previous timer interrupt is a result of Timer Input Capture Event.
PS022828-0413
PRELIMINARY
Timer Control Register Definitions