Z8F042ASJ020EG2156 Datasheet, PDF (80/280 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F082A Series
Product Specification
64
Bit
Description (Continued)
[4]
UART 0 Receive Interrupt Request Enable Low Bit
U0RENL
[3]
UART 0 Transmit Interrupt Request Enable Low Bit
U0TENL
[2:1]
Reserved
These bits are reserved and must be programmed to 00.
[0]
ADC Interrupt Request Enable Low Bit
ADCENL
IRQ1 Enable High and Low Bit Registers
Table 41 describes the priority control for IRQ1. The IRQ1 Enable High and Low Bit reg-
isters, shown in Tables 41 and 42, form a priority-encoded enabling for interrupts in the
Interrupt Request 1 Register.
Table 41. IRQ1 Enable and Priority Encoding
IRQ1ENH[x] IRQ1ENL[x] Priority
0
0
Disabled
0
1
Level 1
1
0
Level 2
1
1
Level 3
Note: x indicates register bits 0–7.
Description
Disabled
Low
Medium
High
PS022828-0413
PRELIMINARY
Interrupt Control Register Definitions