Z8F042ASJ020EG2156 Datasheet, PDF (78/280 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F082A Series
Product Specification
62
Interrupt Request 2 Register
The Interrupt Request 2 (IRQ2) Register, shown in Table 37, stores interrupt requests for
both vectored and polled interrupts. When a request is presented to the interrupt controller,
the corresponding bit in the IRQ2 Register becomes 1. If interrupts are globally enabled
(vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt
Request 2 Register to determine if any interrupt requests are pending.
Table 37. Interrupt Request 2 Register (IRQ2)
Bit
7
Field
RESET
0
R/W
R/W
Address
6
5
Reserved
0
0
R/W
R/W
4
3
PC3I
0
0
R/W
R/W
FC6H
2
PC2I
0
R/W
1
PC1I
0
R/W
0
PC0I
0
R/W
Bit
Description
[7:4]
Reserved
These bits are reserved and must be programmed to 0000.
[3:0]
PCxI
Port C Pin x Interrupt Request
0 = No interrupt request is pending for GPIO Port C pin x.
1 = An interrupt request from GPIO Port C pin x is awaiting service.
Note: x indicates the specific GPIO Port C pin number (0–3).
IRQ0 Enable High and Low Bit Registers
Table 38 describes the priority control for IRQ0. The IRQ0 Enable High and Low Bit reg-
isters, shown in Tables 39 and 40, form a priority-encoded enabling for interrupts in the
Interrupt Request 0 Register.
Table 38. IRQ0 Enable and Priority Encoding
IRQ0ENH[x] IRQ0ENL[x] Priority
0
0
Disabled
0
1
Level 1
1
0
Level 2
1
1
Level 3
Note: x indicates register bits 0–7.
Description
Disabled
Low
Medium
High
PS022828-0413
PRELIMINARY
Interrupt Control Register Definitions