Z8F042ASJ020EG2156 Datasheet, PDF (40/280 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F082A Series
Product Specification
24
Reset Sources
Table 9 lists the possible sources of a system reset.
Table 9. Reset Sources and Resulting Reset Type
Operating Mode Reset Source
Special Conditions
Normal or Halt modes Power-On Reset/Voltage Brown- Reset delay begins after supply voltage
Out
exceeds POR level.
Watchdog Timer time-out
when configured for Reset
None.
RESET pin assertion
All reset pulses less than three system clocks
in width are ignored.
On-Chip Debugger initiated Reset System Reset, except the On-Chip Debugger
(OCDCTL[0] set to 1)
is unaffected by the reset.
Stop Mode
Power-On Reset/Voltage Brown- Reset delay begins after supply voltage
Out
exceeds POR level.
RESET pin assertion
All reset pulses less than the specified analog
delay are ignored. See Table 131 on
page 229.
DBG pin driven Low
None.
Power-On Reset
Z8 Encore! XP F082A Series devices contain an internal Power-On Reset circuit. The
POR circuit monitors the supply voltage and holds the device in the Reset state until the
supply voltage reaches a safe operating level. After the supply voltage exceeds the POR
voltage threshold (V_POR), the device is held in the Reset state until the POR Counter has
timed out. If the crystal oscillator is enabled by the option bits, this time-out is longer.
After the Z8 Encore! XP F082A Series device exits the Power-On Reset state, the eZ8
CPU fetches the Reset vector. Following Power-On Reset, the POR status bit in the Reset
Status (RSTSTAT) Register is set to 1.
Figure 5 displays Power-On Reset operation. See Electrical Characteristics on page 221
for the POR threshold voltage (V_POR).
PS022828-0413
PRELIMINARY
Reset Sources