Z8F042ASJ020EG2156 Datasheet, PDF (231/280 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F082A Series
Product Specification
216
Table 128. eZ8 CPU Instruction Summary (Continued)
Assembly
Mnemonic
Symbolic Operation
Address
Mode
dst src
Opcode(s)
Flags
Fetch Instr.
Cycle Cycle
(Hex) C Z S V D H s
s
JR dst
PC  PC + X
DA
8B
–––––– 2
2
JR cc, dst
if cc is true
DA
PC  PC + X
0B-FB – – – – – – 2
2
LD dst, rc
dst  src
r
IM 0C-FC – – – – – – 2
2
r X(r)
C7
3
3
X(r) r
D7
3
4
r
Ir
E3
2
3
R
R
E4
3
2
R IR
E5
3
4
R IM
E6
3
2
IR IM
E7
3
3
Ir
r
F3
2
3
IR R
F5
3
3
LDC dst, src dst  src
r
Irr
C2
–––––– 2
5
Ir Irr
C5
2
9
Irr
r
D2
2
5
LDCI dst, src
dst  src
r  r + 1
rr  rr + 1
Ir Irr
Irr Ir
C3
–––––– 2
9
D3
2
9
LDE dst, src dst  src
r
Irr
82
–––––– 2
5
Irr
r
92
2
5
LDEI dst, src
dst  src
r  r + 1
rr  rr + 1
Ir Irr
Irr Ir
83
–––––– 2
9
93
2
9
LDWX dst, src dst  src
ER ER 1FE8 – – – – – – 5
4
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
PS022828-0413
PRELIMINARY
eZ8 CPU Instruction Summary