Z8F042ASJ020EG2156 Datasheet, PDF (49/280 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers

Z8 Encore! XP^® F082A Series
Product Specification
33
Halt Mode
Executing the eZ8 CPU’s Halt instruction places the device into Halt Mode, which powers
down the CPU but leaves all other peripherals active. In Halt Mode, the operating charac-
teristics are:
• Primary oscillator is enabled and continues to operate
• System clock is enabled and continues to operate
• eZ8 CPU is stopped
• Program counter (PC) stops incrementing
• Watchdog Timer’s internal RC oscillator continues to operate
• If enabled, the Watchdog Timer continues to operate
• All other on-chip peripherals continue to operate, if enabled
The eZ8 CPU can be brought out of Halt Mode by any of the following operations:
• Interrupt
• Watchdog Timer time-out (interrupt or reset)
• Power-On Reset
• Voltage Brown-Out reset
• External RESET pin assertion
To minimize current in Halt Mode, all GPIO pins that are configured as inputs must be
driven to one of the supply rails (V_CC or GND).
Peripheral-Level Power Control
In addition to the Stop and Halt modes, it is possible to disable each peripheral on each of
the Z8 Encore! XP F082A Series devices. Disabling a given peripheral minimizes its
power consumption.
Power Control Register Definitions
The following sections define the Power Control registers.
Power Control Register 0
Each bit of the following registers disables a peripheral block, either by gating its system
clock input or by removing power from the block. The default state of the low-power
PS022828-0413
PRELIMINARY
Halt Mode