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Z8F042ASJ020EG2156 Datasheet, PDF (57/280 Pages) Zilog, Inc. – High-Performance 8-Bit Microcontrollers
Z8 Encore! XP® F082A Series
Product Specification
41
Table 15. Port Alternate Function Mapping (Non 8-Pin Parts) (Continued)
Port
Pin
Port B3 PB0
Mnemonic
Reserved
Alternate Function Description
Alternate Function
Set Register AFS1
AFS1[0]: 0
ANA0/AMPOUT ADC Analog Input/LPO Output
AFS1[0]: 1
PB1 Reserved
AFS1[1]: 0
ANA1/AMPINN ADC Analog Input/LPO Input (N)
AFS1[1]: 1
PB2 Reserved
AFS1[2]: 0
ANA2/AMPINP ADC Analog Input/LPO Input (P)
AFS1[2]: 1
PB3 CLKIN
External Clock Input
AFS1[3]: 0
ANA3
ADC Analog Input
AFS1[3]: 1
PB4 Reserved
AFS1[4]: 0
ANA7
ADC Analog Input
AFS1[4]: 1
PB5 Reserved
VREF4
PB6 Reserved
ADC Voltage Reference
AFS1[5]: 0
AFS1[5]: 1
AFS1[6]: 0
Reserved
AFS1[6]: 1
PB7 Reserved
AFS1[7]: 0
Reserved
AFS1[7]: 1
Notes:
1. Because there is only a single alternate function for each Port A pin, the Alternate Function Set registers are not
implemented for Port A. Enabling alternate function selections automatically enables the associated alternate
function. See the Port A–D Alternate Function Subregisters (PxAF) section on page 47 for details.
2. Whether PA0/PA6 takes on the timer input or timer output complement function depends on the timer configura-
tion. See the Timer Pin Signal Operation section on page 84 for details.
3. Because there are at most two choices of alternate function for any pin of Port B, the Alternate Function Set
Register AFS2 is not used to select the function. Alternate function selection must also be enabled. See the Port
A–D Alternate Function Subregisters (PxAF) section on page 47 for details.
4. VREF is available on PB5 in 28-pin products and on PC2 in 20-pin parts.
5. Because there are at most two choices of alternate function for any pin of Port C, the Alternate Function Set
Register AFS2 is not used to select the function. Alternate function selection must also be enabled. See the Port
A–D Alternate Function Subregisters (PxAF) section on page 47 for details.
6. Because there is only a single alternate function for the Port PD0 pin, the Alternate Function Set registers are
not implemented for Port D. Enabling alternate function selections automatically enables the associated alter-
nate function. See the Port A–D Alternate Function Subregisters (PxAF) section on page 47 for details.
PS022828-0413
PRELIMINARY
External Clock Setup