Z16C30 Datasheet, PDF (7/86 Pages) Zilog, Inc. – CMOS USC Universal Controller

ZiLOG
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%/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
2+0 (70%6+105
4'5'6 4GUGV KPRWV CEVKXG .QY This signal resets the
device to a known state. The first write to the USC after a
reset accesses the BCR to select additional bus options for
the device.
#5 #FFTGUU 5VTQDG KPRWV CEVKXG .QY This signal is
used in the multiplexed bus modes to latch the address on
the AD lines. The AS signal is not used in the nonmulti-
plexed bus modes and should be tied to V_DD.
&5 &CVC 5VTQDG KPRWV CEVKXG .QY This signal strobes
data out of the device during a read and may strobe an in-
terrupt vector out of the device during an interrupt acknowl-
edge cycle. DS also strobes data into the device on the state
of R/W.
4& 4GCF 5VTQDG KPRWV CEVKXG .QY This signal strobes
data out of the device during a read and may strobe an in-
terrupt vector out of the device during an interrupt acknowl-
edge cycle.
94 9TKVG 5VTQDG KPRWV CEVKXG .QY T h i s
strobes data into the device during a write.
signal
49 4GCF9TKVG KPRWV This signal determines the direc-
tion of data transfer for a read or write cycle in conjunction
with DS.
%5 %JKR 5GNGEV KPRWV CEVKXG .QY This signal selects
the device for access and must be asserted for read and write
cycles, but is ignored during interrupt acknowledge and fly-
by DMA transfers. In the case of a multiplexed bus inter-
face, CS is latched by the rising edge of AS.
#$ %JCPPGN #%JCPPGN $ 5GNGEV KPRWV This signal se-
lects between the two channels in the device. High selects
channel A and Low selects channel B. This signal is sam-
pled and the result is latched during the BCR (Bus Config-
uration Register) write. It programs the sense of the
WAIT/RDY signal appropriate for different bus interfaces.
&% &CVC%QPVTQN 5GNGEV KPRWV This signal, when High,
provides for direct access to the RDR and TDR. In the case
of a multiplexed bus interface, D/% High overrides the ad-
dress provided to the device.
5+6#%- 5VCVWU +PVGTTWRV #EMPQYNGFIG KPRWV CEVKXG
.QY This signal is a status signal that indicates that an in-
terrupt acknowledge cycle is in progress. The device is ca-
pable of returning an interrupt vector that may be encoded
with the type of interrupt pending during this acknowledge
cycle. This signal is compatible with 680X0 family micro-
processors.
2+6#%- 2WNUGF +PVGTTWRV #EMPQYNGFIG KPRWV CEVKXG
.QY This signal is a strobe signal that indicates that an in-
terrupt acknowledge cycle is in progress. The device is ca-
pable of returning an interrupt vector that may be encoded
with the type of interrupt pending during this acknowledge
cycle. PITACK may be programmed to accept a single pulse
or double pulse acknowledge type. This programming is
done in the BCR. With the double pulse type selected, the
first PITACK is recognized but no action takes place. The
interrupt vector is returned on the second pulse if the no vec-
tor option is not selected. The double pulse type is compat-
ible with 8X86 family microprocessors.
9#+64&; 9CKV&CVC 4GCF[ QWVRWV CEVKXG .QY T h i s
signal serves to indicate when the data is available during
a read cycle, when the device is ready to receive data during
a write cycle, and when a valid vector is available during
an interrupt acknowledge cycle. It may be programmed to
function either as a Wait signal or a Ready signal using the
state of the A/$ pin during the BCR write. When A/B is High
during the BCR write, this signal functions as a wait output
and thus supports the READY function of 8X86 family mi-
croprocessors. When A/B is Low during the BCR write, this
signal functions as a ready output and thus supports the
DTACK function of 680X0 family microprocessors.
#& #& #FFTGUU&CVC $WU DKFKTGEVKQPCN CEVKXG
*KIJ VTKUVCVG The AD signals carry addresses to, and
data to and from, the device. When the 16-bit nonmulti-
plexed bus is selected, AD15–AD0 carry data to and from
the device. Addresses are provided using a pointer within
the device that is loaded with the desired register address.
When selecting the 8-bit nonmultiplexed bus (without sep-
arate address) only AD7–AD0 are used to transfer data. The
pointer is used for addressing, with AD15–AD8 unused.
When selecting the 8-bit nonmultiplexed bus (with separate
address), AD7–AD0 are used to transfer data with
AD15–AD8 used as address bus. When the 16-bit multi-
plexed bus is selected, addresses are latched from
AD7–AD0 and data transfers are sixteen bits wide. When
selecting the 8-bit multiplexed bus (without separate ad-
dress) only AD7–AD0 are used to transfer addresses and
data, with AD15–AD8 unused. When the 8-bit multiplexed
bus with separate address is selected, only AD7–AD0 are
used to transfer data, while AD15–AD8 are used as an ad-
dress bus.
+06# +06$ +PVGTTWRV 4GSWGUV QWVRWVU CEVKXG .QY T h e s e
signals indicate that the channel has an interrupt condition
pending and is requesting service. These outputs are NOT
open-drain.
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