Z16C30 Datasheet, PDF (36/86 Pages) Zilog, Inc. – CMOS USC Universal Controller

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The USC internal structure includes two completely inde-
pendent full-duplex serial channels, each with two baud rate
generators, a digital phase-locked loop for clock recovery,
transmit and receive character counters and a full-duplex
DMA interface. The two serial channels share a common
bus interface. The bus interface is designed to provide easy
interface to most microprocessors, whether they employ a
multiplexed or nonmultiplexed, 8-bit or16-bit bus structure.
Each channel is controlled by a set of thirty 16-bit registers,
nearly all of which are readable and writable. There is one
additional 16-bit register in the bus interface used to con-
figure the nature of the bus interface. The BCR functions
are shown in below.
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Both the transmitter and the receiver in the channel are ac-
tually microcoded serial processors. As the data shifts
through the transmit or receive shift register, the microcode
watches for specific bit patterns, counts bits, and at the ap-
propriate time transfers data to or from the FIFOs. The mi-
crocode also checks status and generates status interrupts
as appropriate.
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The functional capabilities of the USC are described from
two different points of view: as a data communications de-
vice, it transmits and receives data in a wide variety of data
communications protocols; as a microprocessor peripheral,
the USC offers such features as read/write registers, a flex-
ible bus interface, DMA interface support and vectored in-
terrupts.
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The USC provides two independent full-duplex channels
programmable for use in any common data communication
protocol. The receiver and transmitter modes are complete-
ly independent, as are the two channels. Each receiver and
transmitter is supported by a 32-byte deep FIFO and a 16-
bit message length counter. All modes allow optional even,
odd, mark or space parity. Synchronous modes allow the
choice of two 16-bit or one 32-bit CRC polynomial. Selec-
tion of from one to eight bits-per-character is available in
both receiver and transmitter, independently. Error and sta-
tus conditions are carried with the data in the receive and
transmit FIFOs to greatly reduce the CPU overhead re-
quired to send or receive a message. Specific, appropriately
timed interrupts are available to signal such conditions as
overrun, parity error, framing error, end-of-frame, idle line
received, sync acquired, transmit underrun, CRC sent, clos-

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