Z16C30 Datasheet, PDF (40/86 Pages) Zilog, Inc. – CMOS USC Universal Controller

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The USC offers the choice of polling, interrupt (vectored
or nonvectored) and block transfer modes to transfer data,
status and control information to and from the CPU.
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All interrupts are disabled. The registers in the USC are au-
tomatically updated to reflect current status. The CPU polls
the Daisy Chain Control Register (DCCR) to determine sta-
tus changes and then reads the appropriate status register
to find and respond to the change in status. USC status bits
are grouped according to function to simplify this software
action.
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When a USC responds to an interrupt acknowledge from
the CPU, an interrupt vector may be placed on the data bus.
This vector is held in the Interrupt Vector Register (IVR).
To speed interrupt response time, the USC modifies three
bits in this vector to indicate which type of interrupt is being
requested.
Each of the six sources of interrupts in each channel of the
USC (Receive Status, Receive Data, Transmit Status,
Transmit Data, I/O Status and Device Status) has three bits
associated with the interrupt source: Interrupt Pending (IP),
Interrupt-Under-Service (IUS) and Interrupt Enable (IE). If
the IE bit for a given source is set, that source can request
interrupts. Note that individual sources within the six
groups also have interrupt enable bits which are set for the
particular source. In addition, there is a Master Interrupt En-
able (MIE) bit in each channel which globally enables or
disables interrupts within the channel.
The other two bits are related to the interrupt priority chain.
A channel in the USC may request an interrupt only when
no higher priority interrupt source is requesting one, e.g.,
when IEI is High for the channel. In this case the channel
activates the INT signal. The CPU then responds with an
interrupt acknowledge cycle, and the interrupting channel
places a vector on the data bus.
In the USC, the IP bit signals that an interrupt request is be-
ing serviced. If an IUS is set, all interrupt sources of lower
priority within the channel and external to the channel are
prevented from requesting interrupts. The internal interrupt
sources are inhibited by the state of the internal daisy chain,
while lower priority devices are inhibited by the IEO output
of the channel being pulled Low and propagated to subse-
quent peripherals. An IUS bit is set during an interrupt ac-
knowledge cycle if there are no higher priority devices re-
questing interrupts.
There are six sources of interrupt in each channel: Receive
Status, Receive Data, Transmit Status, Transmit Data, I/O
Status and Device Status, prioritized in that order within the
channel. There are six sources of Receive Status interrupt,
each individually enabled: exited hunt, idle line,
break/abort, code violation/end-of-transmission/end-of-
frame, parity error and overrun error. The Receive Data in-
terrupt is generated whenever the receive FIFO fills with
data beyond the level programmed in the Receive Interrupt
Control Register (RICR).
There are six sources of Transmit Status interrupt, each in-
dividually enabled: preamble sent, idle line sent, abort sent,
end-of-frame/end-of-transmission sent, CRC sent and un-
derrun error. The Transmit Data interrupt is generated
whenever the transmit FIFO empties below the level pro-
grammed in the Transmit Interrupt Control Register
(TICR). The I/O Status interrupt serves to report transitions
on any of six pins. Interrupts are generated on either or both
edges with separate selection and enables for each pin. The
pins programmed to generate I/O Status interrupts are RxC,
TxC, RxREQ, TxREQ, DCD and CTS. These interrupts are
independent of the programmed function of the pins. The
Device Status interrupt has four separately enabled sources:
receive character count FIFO overflow, DPLL sync ac-
quired, BRG1 zero count and BRGO zero count.
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The USC accommodates block transfers through DMA
through the RxREQ, TxREQ, RxACK and TxACK pins.
The RxREQ signal is activated when the fill level of the re-
ceive FIFO exceeds the value programmed in the RICR. The
DMA may respond with either a normal bus transaction or
by activating the RxACK pin to read the data directly (fly-
by transfer). The TxREQ signal is activated when the empty
level of the transmit FIFO falls below the value pro-
grammed in the TICR. The DMA may respond either with
a normal bus transaction or by activating the TxACK pin
to write the data directly (fly-by transfer). The RxACK and
TxACK pin functions for this mode are controlled by the
Hardware Configuration Register (HCR). Then using the
RxACK and TxACK pins to transfer data, no chip select is
necessary; these are dedicated strobes for the appropriate
FIFO.

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