Z16C30 Datasheet, PDF (15/86 Pages) Zilog, Inc. – CMOS USC Universal Controller

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The USC interface timing is similar to that found on a static
RAM, except that it is much more flexible. Up to eight sep-
arate timing strobe signals may be present on the interface:
DS, RD, WR, PITACK, RxACKA, RxACKB, TxACKA
and TxACKB. Only one of these timing strobes may be ac-
tive at any time. Should the external logic activate more than
one of these strobes at the same time the USC will enter a
pre-reset state that is only exited by a hardware reset. Do
not allow overlap of timing strobes. The timing diagrams,
beginning on the next page, illustrate the different bus trans-
actions possible, with the necessary setup, hold and delay
times.
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