Z16C30 Datasheet, PDF (41/86 Pages) Zilog, Inc. – CMOS USC Universal Controller

ZiLOG
<%
%/15 75% 7PKXGTUCN 5GTKCN %QPVTQNNGT
241)4#//+0)
The registers in each USC channel are programmed by the
system to configure the channels. Before this can occur,
however, the system must program the bus interface by writ-
ing to the Bus Configuration Register (BCR). The BCR has
no specific address and is only accessible immediately after
a hardware reset of the device. The first write to the USC,
after a hardware reset, programs the BCR. From that time
on, the normal channel registers may be accessed. No spe-
cific address need be presented to the USC for the BCR write
because the first write after a hardware reset is automatically
programmed for the BCR.
In the multiplexed bus case, all registers are directly ad-
dressable through the address latched by AS at the begin-
ning of a bus transaction. The address is decoded from either
AD6–AD0 or AD7–AD1. This is controlled by the Shift
Right/Shift Left bit in the BCR. The address maps for these
two cases are shown in Table 2. The D/C pin is still used
to directly access the receive and transmit data registers
(RDR and TDR) in the multiplexed bus; if D/C is High the
address latched by AS is ignored and an access of RDR or
TDR is performed.
In the nonmultiplexed bus case, the registers in each channel
are accessed indirectly using the address pointer in the
Channel Command/Address Register (CCAR) in each
channel. The address of the desired register is first written
to the CCAR and then the selected register is accessed; the
pointer in the CCAR is automatically cleared after this ac-
cess. The RDR and TDR are accessed directly using the D/C
pin, without disturbing the contents of the pointer in the
CCAR.
6CDNG  /WNVKRNGZGF $WU #FFTGUU #UUKIPOGPVU
#FFTGUU 5KIPCN
$[VG9QTF #EEGUU
#FFTGUU 
#FFTGUU 
#FFTGUU 
#FFTGUU 
#FFTGUU 
7RRGT.QYGT $[VG 5GNGEV
5JKHV .GHV
#&
#&
#&
#&
#&
#&
#&
5JKHV 4KIJV
#&
#&
#&
#&
#&
#&
#&
There are two important things to note about the USC. First,
the Channel Reset bit in the CCAR places the channel in
the reset state. To exit this reset state either a word of all
zeros must be written to the CCAR (16-bit bus) or a byte
of all zeros must be written to the lower byte of the CCAR
(8-bit bus). The second thing to note is that after reset, the
transmit and receive clocks are not connected. The first
thing that should be done in any initialization sequence is
a write to the Clock Mode Control Register (CMCR) to se-
lect a clock source for the receiver and transmitter.
The register addressing is shown in Table 3 while the bit
assignments for the registers are shown in Figure 29.
&55%%