Z16C30 Datasheet, PDF (39/86 Pages) Zilog, Inc. – CMOS USC Universal Controller

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allow the CPU to determine message boundaries in mem-
ory. Similarly, the transmit character counter is loaded ei-
ther under software control or automatically at the begin-
ning of a transmit message. The counter is decremented with
each write to the transmit FIFO. When the counter has dec-
remented to 0, and that byte is sent, the transmitter auto-
matically terminates the message in the appropriate fashion
(usually CRC and the closing flag or sync character) without
requiring CPU intervention.
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Each channel in the USC contains two baud rate generators.
Each generator consists of a 16-bit time constant register
and a 16-bit down counter. In operation, the counter decre-
ments with each baud rate generator clock, with the time
constant automatically reloaded when the count reaches ze-
ro. The output of the baud rate generator toggles when the
counter reaches a count of one-half of the time constant and
again when the counter reaches zero.A new time constant
may be written at any time but the new value will not take
effect until the next load of the counter. The outputs of both
baud rate generators are sent to the clock multiplexer for use
internally or externally. The baud rate generator output fre-
quency is related to the baud rate generator input clock fre-
quency by the following formula:
Output frequency = Input frequency/(time constant + 1).
This allows an output frequency in the range of 1 to 1/65536
of the input frequency, inclusive.
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Each channel in the USC contains a Digital Phase-Locked
Loop (DPLL) to recover clock information from a data
stream with NRZI or Biphase encoding. The DPLL is driven
by a clock that is nominally 8, 16 or 32 times the receive
data rate. The DPLL uses this clock, along the data stream,
to construct a clock for the data. This clock may then be rout-
ed to the receiver, transmitter, or both, or to a pin for use
externally. In all modes, the DPLL counts the input clock
to create nominal bit times. As the clock is counted, the
DPLL watches the incoming data stream for transitions.
Whenever a transition is detected, the DPLL makes a count
adjustment (during the next counting cycle), to produce an
output clock which tracks the incoming bit cells. The DPLL
provides properly phased transmit and receive clocks to the
clock multiplexer.
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Each channel contains two 5-bit counters, which are pro-
grammed to divide an input clock by 4, 8, 16 or 32. The in-
puts of these two counters are sent to the clock multiplexer.
The counters are used as prescalers for the baud rate gen-
erators, or to provide a stable transmit clock from a common
source when the DPLL is providing the receive clock.
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The clock multiplexer in each channel selects the clock
source for the various blocks in the channel and selects an
internal clock signal to potentially be sent to either the RxC
or TxC pin.
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The USC can be programmed for local loopback or auto
echo operation. In local loopback, the output of the trans-
mitter is internally routed to the input of the receiver. This
allows testing of the USC data paths without any external
logic. Auto echo connects the RxD pin directly to the TxD
pin. This is useful for testing serial links external to the USC.
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