Z16C30 Datasheet, PDF (37/86 Pages) Zilog, Inc. – CMOS USC Universal Controller

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ing sync/flag sent, abort sent, idle line sent and preamble
sent. In addition, several useful internal signals such as re-
ceive FIFO load, received sync, transmit FIFO read and
transmission complete may be sent to pins for use by ex-
ternal circuitry.
#U[PEJTQPQWU /QFG The receiver and transmitter can
handle data at a rate of 1/16, 1/32, or 1/64 the clock rate.
The receiver rejects start bits less than one-half a bit time
and will not erroneously assemble characters following a
framing error. The transmitter is capable of sending one,
two, or anywhere in the range of 1/16 to two stop bits per
character in 1/16 bit increments.
'ZVGTPCN 5[PE /QFG The receiver is synchronized to the
receive data stream by an externally-supplied signal on a
pin for custom protocol applications.
+UQEJTQPQWU /QFG Both transmitter and receiver may op-
erate on start-stop (async) data using a 1x clock. The trans-
mitter can send one or two stop bits.
#U[PEJTQPQWU 9KVJ %QFG 8KQNCVKQPU This is similar to
Isochronous mode except that the start bit is replaced by a
three bit-time code violation pattern as in MIL-STD 1553B.
The transmitter can send zero, one or two stop bits.
/QPQU[PE /QFG In this mode, a single character is used
for synchronization. The sync character can be either eight
bits long with an arbitrary data character length, or pro-
grammed to match the data character length. The receiver
is capable of automatically stripping sync characters from
the received data stream. The transmitter may be pro-
grammed to automatically send CRC on either an underrun
or at the end of a programmed message length.
$KU[PE /QFG This mode is identical to monosync mode
except that character synchronization requires two succes-
sive characters for synchronization. The two characters
need not be identical.
*&.% /QFG In this mode, the receiver recognizes flags,
performs optional address matching, accommodates ex-
tended address fields, 8- or 16-bit control fields and logical
control fields, performs zero deletion and CRC checking.
The receiver is capable of receiving shared-zero flags, rec-
ognizes the abort sequence and can receive arbitrary length
messages. The transmitter automatically sends opening and
closing flags, performs zero insertion and can be pro-
grammed to send an abort, an extended abort, a flag or CRC
and a flag on transmit underrun. The transmitter can also
automatically send the closing flag with optional CRC at
the end of a programmed message length. Shared-zero flags
are selected in the transmitter and a separate character
length may be programmed for the last character in the
frame.
$KU[PE 6TCPURCTGPV /QFG In this mode, the synchroniza-
tion pattern is DLE–SYN, programmable selected from ei-
ther ASCII or EBCDIC encoding. The receiver recognizes
control character sequences and automatically handles
CRC calculation without CPU intervention. The transmitter
can be programmed to send either SYN, DLE–SYN,
CRC–SYN, or CRC–DLE–SYN upon underrun and can au-
tomatically send the closing DLE–SYN with optional CRC
at the end of a programmed message length.
0$+2 /QFG This mode is identical to async except that the
receiver checks for the status of an additional address/data
bit between the parity bit and the stop bit. The value of this
bit is FIFO’ed along with the data. This bit is automatically
inserted in the transmitter with the value that is FIFO’ed
with the transmit data.
 /QFG This mode implements the data format of
IEEE 802.3 with 16-bit address compare. In this mode,
DCD and CTS are used to implement the carrier sense and
collision detect interactions with the receiver and transmit-
ter.
5NCXGF /QPQU[PE /QFG This mode is available only in
the transmitter and allows the transmitter (operating as
though it were in monosync mode) to send data that is byte-
synchronous to the data being received by the receiver.
*&.% .QQR /QFG This mode is also available only in the
transmitter and allows the USC to be used in an HDLC loop
configuration. In this mode, the receiver is programmed to
operate in HDLC mode so that the transmitter echoes re-
ceived messages. Upon receipt of a particular bit pattern (ac-
tually a sequence of seven consecutive ones) the transmitter
breaks the loop and inserts its own frame(s).
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The USC may be programmed to encode and decode the se-
rial data in any of eight different ways as shown in Figure
28. The transmitter encoding method is selected indepen-
dently of the receiver decoding method.
04< In NRZ, a 1 is represented by a High level for the du-
ration of the bit cell and a 0 is represented by a Low level
for the duration of the bit cell.
04<$ Data is inverted from NRZ.
04<+/CTM In NRZI-Mark, a 1 is represented by a transi-
tion at the beginning of the bit cell. That is, the level present
in the preceding bit cell is reversed. A 0 is represented by
the absence of a transition at the beginning of the bit cell.
04<+5RCEG In NRZI-Space, a 1 is represented by the ab-
sence of a transition at the beginning of the bit cell. That is,
the level present in the preceding bit cell is maintained. A
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