Z16C30 Datasheet, PDF (2/86 Pages) Zilog, Inc. – CMOS USC Universal Controller

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(20 MHz when using the DPLL, BRG, or CTR) and data
transfer rates as high as 10 Mbits/sec full duplex.
The USC handles asynchronous formats, synchronous
byte-oriented formats such as BISYNC and synchronous
bit-oriented formats such as HDLC. This device supports
virtually any serial data transfer application.
The device can generate and check CRC in any synchronous
mode and can be programmed to check data integrity in var-
ious modes. The USC also has facilities for modem controls
in both channels. In applications where these controls are
not needed, the modem controls may be used for general-
purpose I/O. The same is true for most of the other pins in
each channel.
Interrupts are supported with a daisy-chain hierarchy, with
the two channels having completely separate interrupt
structures.
High-speed data transfers through DMA are supported by
a Request/Acknowledge signal pair for each receiver and
transmitter. The device supports automatic status transfer
through DMA and also allows device initialization under
DMA control.
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0QVG When written to, all reserved bits must be programmed
to 0.
To aid the designer in efficiently programming the USC,
support tools are available. The Technical Manual describes
in detail all features presented in this Product Specification
and gives programming sequence hints. The Programmer’s
Assistant is a MS-DOS disk-based programming initializa-
tion tool to be used in conjunction with the Technical Man-
ual. There are also available assorted application notes and
development boards to assist the designer in the hard-
ware/software development.
All Signals with an overline, are active Low. For example:
B/W, in which WORD is active Low, and B/W, in which
BYTE is active Low.
Power connections follow these conventional descriptions:
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