Z86E6116PSC Datasheet, PDF (65/69 Pages) Zilog, Inc. – Z86E61/Z86E63 CMOS Z8 16K/32K EPROM Microcontroller

Z86E61/E63
CMOS Z8 16K/32K EPROM Microcontroller
61
OPCODE MAP
Lower Nibble (Hex)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
6.6 6.5
6.5
8.5 10.5 10.5 10.5 10.5 6.5
DEC DEC ADD ADD ADD ADD ADD ADD LD
6.5 12/10.5 12/0.0
LD DJNZ JA
6.5 12/10.0 6.5
LD
JP
INC
R1 IR1 r1, r2 r1, Ir2 R2, R1 IR2, R1 R1, 1M R1, 1M r1,R2 r2, R1 r1, RA cc, RA r1, 1M cc, DA r1
1
6.5
6.5 6.5
RLC RLC ADC
6.5 10.5 10.5 10.5 10.5
ADC ADC ADC ADC ADC
R1
IR1 r1, r2 r1, Ir2 R2, R1 IR2,R1 R1, 1M R1, 1M
6.5
6.6 6.5
0.5
10.5 10.5 10.5 10.5
2
INC
WC SUB SUB SUB SUB SUB BUB
R1
IR1 r1, r2 r1, Ir2 R2, R1 IR2, R1 R2, 1M IR1, 1M
3
6.5
JP
6.1
6.5
6.5 ^{10.5 10.5 10.5 10.5}
SRP SBC _SBC SBC SBC SBC SBC
IRR1 1M r1, r2 _{r1, Ir2} R2, R1 IR2, R1 R1, 1M IR1, 1M
8.5 8.5
6.5 6.5 10.5 10.5 10.5
4
DA
DA
OR OR OR OR OR
R1 IR1 r1, r2 r1, Ir2 R2, R1 IR2, R1 R1, 1M
10.5 10.5
6.5 6.5 10.5 10.5 10.5 10.5
5 POP POP AND AND AND AND AND AND
R1
IR1
r1, r2 r1, Ir2 R2, R1 IR2, R1 R1, 1M IR1, 1M
6.5 6.5
6.5
6.5
10.5 10.5 10.5 10.5
6 COM COM TCM TCM TCM TCM TCM TCM
R1 IR1 r1, r2 r1, Ir2 R2, R1 IR2, R1 R1, 1M IR1, 1M
10/12.1 10/12.1 6.5
6.5 10.5 10.5 10.5 10.5
7 PUSH PUSH TM
TM
TM
TM TM
TM
R2
IR2 r1, r2 r1, Ir2 R2, R1 IR2, R1 R1, 1M IR1, 1M
10.5 10.5 12.0 18.0
8 DECW DECW LDE LDEI
RR1
IR1 r1, Irr2 r1, Irr2
6.5
9 RL
R1
6.5
12.0 18.0
RL
LDE LDEI
IR1 r1, Irr2 r1, Irr2
10.5 10.5 6.5
6.5
10.5 10.5 10.5 10.5
A INCW INCW CP
CP
CP CP CP CP
RR1 IR1 r1, r2 r1, Ir2 R2, R1 IR2, R1 R1, 1M IR1, 1M
6.5
6.5
6.5
6.5
10.5 10.5 10.5 10.5
B CLR CLR XOR XOR XOR XOR XOR XOR
R1
IR1 r1, r2 r1, Ir2 R2, R1 IR2, R1 R1, 1M IR1, 1M
6.0
STOP
7.0
HALT
6.1
DI
6.1
EI
14.0
RET
16.0
IRET
6.5 6.5
C RRC RRC
R1 IR1
12.0 18.0
LDC LDC
r1, Irr2 Ir1, Irr2
10.5
LD
r1, x, R2
6.5
RCF
6.5
D SRA
R1
6.5 12.0 18.0 20.0
SRA LDC LDCI CALL*
IR1 r1, Irr2 Ir1, Irr2 IRR1
20.0 10.5
CALL LD
DA r2, x, R1
6.5 6.5
E
RR RR
R1 IR1
6.5
10.5 10.5 10.5 10.5
LD
LD
LD LD
LD
r1, IR2 R2, R1 IR2, R1 R1, 1M IR1, 1M
8.5 8.5
F SWAP SWAP
R1 IR1
6.5
LD
Ir1, r2
10.5
LD
R2, IR1
6.5
SCF
6.5
CCF
6.0
NOP
2
Execution
Cycles
Lower
Opcode
Nibble
Upper
Opcode
Nibble
4
A
10.5
CP
R1, R2
3
Bytes per Instruction
Pipeline
Cycles
Mnemonic
First
Operand
Second
Operand
2
3
1
Legend:
R = 8-bit Address
r = 4-bit Address
R1 or r1 = Dst Address
R2 or r2 = Src Address
Sequence:
Opcode, First Operand,
Second Operand
Note: Blank areas not defined
*2-byte instruction appears as
a 3-byte instruction
Figure 47. Opcode Map
PS014401-1001