Z86E6116PSC Datasheet, PDF (21/69 Pages) Zilog, Inc. – Z86E61/Z86E63 CMOS Z8 16K/32K EPROM Microcontroller

Z86E61/E63
CMOS Z8 16K/32K EPROM Microcontroller
17
UART OPERATION
Port 3 lines, P37 and P30, are programmed as serial I/0 lines for full-duplex serial
asynchronous receiver/transmitter operation. The bit rate is controlled by Counter/
Timer0.
The Z86E61/E63 automatically adds a start bit and two stop bits to transmitted
data (Figure 10). Odd parity is also available as an option. Eight data bits are
always transmitted, regardless of parity selection. If parity is enabled, the eighth
bit is the odd parity bit. An interrupt request (IRQ4) is generated on all transmitted
characters.
Received data must have a start bit, eight data bits, and at least one stop bit. If
parity is on, bit 7 of the received data is replaced by a parity error flag. Received
characters generate the IRQ3 interrupt request.
Transmitted Data (No Parity)
SP SP D7 D6 D5 D4 D3 D2 D1 D0 ST
Received Data (No Parity)
SP D7 D6 D5 D4 D3 D2 D1 D0 ST
Start Bit
Eight Data Bits
Two Stop Bits
Start Bit
Eight Data Bits
One Stop Bit
Transmitted Data (With Parity)
SP SP P D6 D5 D4 D3 D2 D1 D0 ST
Received Data (With Parity)
SP P D6 D5 D4 D3 D2 D1 D0 ST
Start Bit
Odd Parity
Two Stop Bits
Start Bit
Seven Data Bits
Parity Error Flag
One Stop Bit
Figure 10. Serial Data Formats
Auto Latch
The Auto Latch puts valid CMOS levels on all CMOS inputs that are not externally
driven. This reduces excessive supply current flow in the input buffer when it is not
driven by any source.
Note:
P33-P30 inputs differ from the Z86C61/C63 in that there is no
clamping diode to V_CC because of the EPROM high voltage
detection circuits. Exceeding the VIH maximum specification
during standard operating mode may cause the device to enter
EPROM mode.
PS014401-1001