Z86E6116PSC Datasheet, PDF (30/69 Pages) Zilog, Inc. – Z86E61/Z86E63 CMOS Z8 16K/32K EPROM Microcontroller

Z86E61/E63
CMOS Z8 16K/32K EPROM Microcontroller
26
must execute a NOP (opcode = 0FFH) immediately before the appropriate SLEEP
instruction. i.e.,
FF
NOP
; clear the pipeline
6F
STOP
; enter STOP mode
or
FF
NOP
; clear the pipeline
7F
HALT
; enter HALT mode
PROGRAMMING
Z86E61/E63 User Modes
The Z86E61/E63 uses separate AC timing cycles for the different User Modes
available. Table 22 on page 27 shows the Z86E61/E63 User Modes. Table 23 on
page 28 shows the timing of the programming waveforms.
User MODE 1 EPROM Read
The Z86E61 /E63 EPROM read cycle is provided so that the user may read the
Z86E61 /E63 as a standard 27128 (E61) or 27256 (E63) EPROM. This is accom-
plished by driving the EPM pin (P32) to VH and activating CE and OE. PGM
remains inactive. This mode is not valid after execution of an EPROM protect
cycle. Timing for the EPROM read cycle is shown in Figure 18.
User MODE 2 EPROM Program
The Z86E61/E63 Program function conforms to the Intelligent programming algo-
rithm. The device is programmed with V_cc, at 6.0V and V_PP = 12.5V. Programming
pulses are applied in 1 ms increments to a maximum of 25 pulses before proper
verification. After verification, a programming pulse of three times the duration of
the cycles necessary to program the device is issued to ensure proper program-
ming. After all addresses are programmed, a final data comparison is executed
and the programming cycle is complete. Timing for the Z86E61/E63 programming
cycle is shown in Figure 18.
User Mode 3: PROM Verify
The Program Verify cycle is used as part of the intelligent programming algorithm
to insure data integrity under worst-case conditions. It differs from the EPROM
Read cycle in that Vpp is active and V_CC must be driven to 6.0V. Timing is shown
in Figure 18.
PS014401-1001