Z86E6116PSC Datasheet, PDF (31/69 Pages) Zilog, Inc. – Z86E61/Z86E63 CMOS Z8 16K/32K EPROM Microcontroller

Z86E61/E63
CMOS Z8 16K/32K EPROM Microcontroller
27
User Modes 4 and 5: EPROM and RAM Protect
To extend program security, EPROM and RAM protect cycles are provided for the
Z86E61/E63. Execution of the EPROM protect cycle prohibits proper execution of
the EPROM Read, EPROM Verify, and EPROM programming cycles. Execution
of the RAM protect cycle disables accesses to the upper 128 bytes of register
memory (excluding mode and configuration registers), but first the user’s program
must set bit 6 of the IMR (R251). Timing is shown in Figure 20 and Figure 21.
User Modes. Table 6 shows the programming voltage of each mode of the
Z86E61/E63.
Table 22. OTP Programming^a
User/Test Mode
Device Pin No.
User Modes
EPROM Read
Program
Program Verify
EPROM Protect
RAM Protect
P33
V_PP
V_IH
V_PPb
V_PPb
V_PPb
V_PP
Device Pins
P32 P30 P31
EPM
V_Hc
X
X
V_H
X
CE
V_ILd
V_IL
V_IL
V_H
V_H
OE
V_IL
V_IHe
V_IL
V_IH
V_IH
P20
PGM
V_IH
V_IL
V_IH
V_IL
V_IL
ADDR V_CC
Addr 5.0V
Addr 6.0V
Addr
XX^f
XX^f
6.0V
6.0V
6.0V
Port 1
CNFG
Data
Out
In
Out
XX
XX
a. I_PP during programming = 40 mA maximum.
I_CC during programming, verify, or read = 40 mA maximum.
b. V_PP = 12.0 ± 0.5 V.
c. V_H = 12.0 ± 0.5 V
d. V_IL = 0 V
e. V_IH = 5 V.
f. XX = Irrelevant.
Z86E63 Signal Description for EPROM Program/Read
The following signals are required to correctly program or read the Z86E63
device.
ADDR
The address must remain stable throughout the program read cycle.
DATA
The I/O data bus must be stable during programming (OE High, PGM Low, VPP
High). During read the data bus outputs data.
PS014401-1001