Z86E6116PSC Datasheet, PDF (28/69 Pages) Zilog, Inc. – Z86E61/Z86E63 CMOS Z8 16K/32K EPROM Microcontroller

Z86E61/E63
CMOS Z8 16K/32K EPROM Microcontroller
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or individually enables or disables the six interrupt requests. When more than one
interrupt is pending, priorities are resolved by a programmable priority encoder
that is controlled by the Interrupt Priority register (refer to Table 21 on page 16).
All Z86E61/E63 interrupts are vectored through locations in the program memory.
When an interrupt machine cycle is activated, an interrupt request is granted.
Thus, this disables all of the subsequent interrupts, saves the Program Counter
and Status Flags, and then branches to the program memory vector location
reserved for that interrupt. This memory location and the next byte contain the 16-
bit address of the interrupt service routine for that particular interrupt request.
To accommodate polled interrupt systems, interrupt inputs are masked and the
Interrupt Request register is polled to determine which of the interrupt requests
need service. Software initialized interrupts are supported by setting the appropri-
ate bit in the Interrupt Request Register (IRQ).
Internal interrupt requests are sampled on the falling edge of the last cycle of
every instruction, and the interrupt request must be valid 5TpC before the falling
edge of the last clock cycle of the currently executing instruction.
IRQ0-IRQ5
IRQ
IMR
6
Global
Interrupt
Enable
IPR
Interrupt
Request
PRIORITY
LOGIC
Vector Select
Figure 16. Interrupt Block Diagram
For the ROMless mode, when the device samples a valid interrupt request, the
next 48 (external) clock cycles are used to prioritize the interrupt, and push the
two PC bytes and the FLAG register on the stack. The following nine cycles are
used to fetch the interrupt vector from external memory. The first byte of the inter-
rupt service routine is fetched beginning on the 58th TpC cycle following the inter-
PS014401-1001