Z86E6116PSC Datasheet, PDF (32/69 Pages) Zilog, Inc. – Z86E61/Z86E63 CMOS Z8 16K/32K EPROM Microcontroller

Z86E61/E63
CMOS Z8 16K/32K EPROM Microcontroller
28
XCLK
A clock is required to clock the RESET signal into the registers before program-
ming.
A constant clock can be applied, or the XCLK input can be toggled a minimum of
12 cycles before any programming or verify function begins. The maximum clock
frequency to be applied when in the EPROM mode is 12 MHz.
RESET
The reset input can be held to a constant Low or High value throughout normal
programming. It must be held High to program the EPROM protect option bit.
Also, any time the RESET input changes state the XCLK must be clocked a mini-
mum of 12 times to clock the RESET through the reset filter.
OE
When the device is placed in EPROM mode, the OE input also serves as the pre-
charge for the sense amp. The precharge signal should be Low for the first half of
the stable address and High for the second half. The PRECHG signal is inverted
from the OE signal so the OE should be High on the first half and Low on the sec-
ond half, or stable address. The EPROM output data should be sampled during
the second half of stable address.
The access time of the EPROM is defined in later sections. This two part calcula-
tion of access time is required because this is a precharged sense amp with a pre-
charge clock.
Table 23. Timing of Programming Waveforms
Parameters
1
2
3
4
5
6
7
8
9
10
Name
Address Setup Time
Data Setup Time
V_PP Setup
V_CC Setup Time
Chip Enable Setup Time
Program Pulse Width
Data Hold Time
OE Setup Time
Data Access Time
Data Output Float Time
Min
2
2
2
2
2
0.95
2
2
Max Units
µs
µs
µs
µs
µs
ms
µs
µs
200
ns
100
ns
PS014401-1001