Z86E6116PSC Datasheet, PDF (16/69 Pages) Zilog, Inc. – Z86E61/Z86E63 CMOS Z8 16K/32K EPROM Microcontroller

Z86E61/E63
CMOS Z8 16K/32K EPROM Microcontroller
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On the fifth clock after the RESET is detected, an internal RST signal is latched
and held for an internal register count of 18 external clocks, or for the duration of
the external RESET, whichever is longer. During the reset cycle, DS is held active
Low while AS cycles at a rate of TpC/2. When RESET is deactivated, program
execution begins at location 000C (HEX). Power-up reset time must be held low
for 50 ms, or until V_CC is stable, whichever is longer.
Port 0 (P07-P00)
Port 0 is an 8-bit, nibble programmable, bidirectional, TTL compatible port. These
eight I/O lines can be configured under software control as a nibble I/O port, or as
an address port for interfacing external memory. When used as an I/O port, Port 0
may be placed under handshake control. In this configuration, Port 3, lines P32
and P35 are used as the handshake control DAV0 and RDY0 (Data Available and
Ready). Handshake signal assignment is dictated by the I/O direction of the upper
nibble P07-P04. The lower nibble must have the same direction as the upper nib-
ble to be under handshake control.
For external memory references, Port 0 can provide address bits A11-A8 (lower
nibble) or A15-A8 (lower and upper nibbles) depending on the required address
space. If the address range requires 12 bits or less, the upper nibble of Port 0 can
be programmed independently as I/O while the lower nibble is used for address-
ing. If one or both nibbles are needed for I/O operation, they must be configured
by writing to the Port 0 Mode register.
In ROMless mode, after a hardware reset, Port 0 lines are defined as address
lines A15-A8, and extended timing is set to accommodate slow memory access.
The initialization routine can include reconfiguration to eliminate this extended tim-
ing mode (Figure 8).
Port 1 (P17-P10)
Port 1 is an 8-bit, byte programmable, bidirectional, TTL compatible port. It has
multiplexed Address (A7-A0) and Data (D7-D0) ports. For Z86E61/E63, these
eight I/O lines can be programmed as input or output lines or are configured under
software control as an address/data port for interfacing external memory. When
used as an I/O port, Port 1 can be placed under handshake control. In this config-
uration, Port 3 lines, P33 and P34, are used as the handshake controls RDY1 and
DAV1.
Memory locations greater than 16384 (E61) or 32768 (E63) are referenced
through Port 1. To interface external memory, Port 1 must be programmed for the
multiplexed Address/ Data mode. If more than 256 external locations are required,
Port 0 must output the additional lines.
PS014401-1001