Z87C33 Datasheet, PDF (52/72 Pages) Zilog, Inc. – CMOS Z8® MCU Consumer Controller Processor

Z87C33
CMOS Z8“ MCU Consumer Controller Processor
46
Stop-Mode Recovery Register 2
The Stop-Mode Recovery Register, SMR2, controls additional Port 2 clocking
functions. WRITE and reset states for bits D7–D0 are listed in Table 34.
Table 34. Stop-Mode Recovery Register 2—SMR2 0Dh/R13 Bank Fh: WRITE ONLY
Bit
D7
D6 D5
D4
D3
D2
D1
D0
R/W
W
W
W
W
W
W
W
W
Reset
X
X
X
X
X
X
0
0
Note: W = Write, X = Indeterminate.
Bit
Bit
Position Field
Reset
R/W State Description
D7–D2 Reserved
W
X Reserved—must be 0
D1–D0 STOP Mode
W
00 Stop-Mode Recovery Source 2*
00: POR only
01: AND P20, P21, P22, P23
10: AND P20, P21, P22, P23, P24, P25,
P26, P27
11: Reserved
Note: For the Stop-Mode Recovery Source, either SMR or SMR2 can be selected. If SMR2 is used
to select the Stop-Mode Recovery Source, bits D4–D2 of SMR must be 0. Not used in
conjunction with SMR Source.
Watch-Dog Timer Mode Register
The Watch-Dog Timer Mode Register, WDTMR, controls Watch-Dog Timer func-
tions. WRITE and reset states for bits D7–D0 are listed in Table 35.
Table 35. Watch-Dog Timer Mode Register—WDTMR 0Fh/R15 Bank Fh: WRITE ONLY
Bit
D7
D6 D5
D4
D3
D2
D1
D0
R/W
W
W
W
W
W
W
W
W
Reset
X
X
X
0
1
1
0
1
Note: W = Write, X = Indeterminate.
PS015601-1003