Z87C33 Datasheet, PDF(31/72 Page) Zilog, Inc. – CMOS Z8® MCU Consumer Controller Processor

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Z87C33 Datasheet, PDF (31/72 Pages) Zilog, Inc. – CMOS Z8® MCU Consumer Controller Processor

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Z87C33

CMOS Z8â MCU Consumer Controller Processor

External Clock Divide-by-Two (D1). This bit can eliminate the oscillator divide-by-

two circuitry. When this bit is 0, the system clock (SCLK) and timer clock (TCLK)

are equal to the external clock frequency divided by 2. The SCLK is equal to the

external clock frequency when this bit is set (D1 = 1). Using this bit together with

D7 of PCON further helps lower EMI (that is, D7 (PCON) = 0, D1 (SMR) = 1). The

default setting is 0. Maximum external clock frequency is 4 MHz when SMR bit D1

= 1 where SCLK & TCLK = XIN.

Stop-Mode Recovery Source (D2, D3, and D4). These three bits of the SMR specify

the wake-up source of the Stop-Mode Recovery (Figure and Stop-Mode Recov-

ery Source). When the Stop-Mode Recovery Sources are selected in this register,

then SMR2 register bits D0,D1 must be set to 0.

Note: If the Port 2 pin is configured as an output, this output level is

read by the SMR circuitry.

VDD D1 D0

SMR2

P20

P23

VDD

D4 D3 D2

0 00

D4 D3 D2

SMR

P30

SMR 0 0 0

0 10

SMR 1 0

0 SMR 1 0 1

P31

0 11

P32

P33

P20

P27

P23

D1 D0

SMR2 0 1

P20

P27

D4 D3 D2

SMR 1 1 0

P20

P27

Stop-Mode Recovery Edge

Select (SMR)

P33 From Pads

Digital/Analog Mode

Select (P3M)

Figure 13.Stop-Mode Recovery Source

SMR2 D1 D0

D4 D3 D2

SMR 1 1 1

To POR

RESET

X To P33

Data Latch

and IRQ1

PS015601-1003

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