Z87C33 Datasheet, PDF (34/72 Pages) Zilog, Inc. – CMOS Z8® MCU Consumer Controller Processor

Z87C33
CMOS Z8“ MCU Consumer Controller Processor
28
Table 12. Watch-Dog Timer Mode Register—WDTMR 0Fh/R15: WRITE ONLY
Bit
D7
D6 D5
D4
D3
D2
D1
D0
R/W
W
W
W
W
W
W
W
W
Reset
X
X
X
0
1
1
0
1
Note: R = Read, W = Write, X = Indeterminate.
Bit/ Bit
Field Position
Reset
R/W State Description
D7–D5 Reserved
W
X Reserved—must be 0
D4
X_IN
D3
WDT
W
0 XIN/INT RC Select for WDT
0: On-Board RC
1: X_IN
W
1 WDT During STOP
D2
WDT
W
1 WDT During HALT
D1–D0 WDT Tap
W
01 WDT Tap Int RC OSC System Clock
00:
3.5 ms
128 SCLK
01:
7.0 ms
256 SCLK
10:
14.0 ms
512 SCLK
11:
56.0 ms
2048 SCLK
Note: Not used in conjunction with SMR Source.
WDT Time Select (D0,D1). Selects the WDT time period and is configured as indi-
cated in Table 14.
Table 13. WDT Time Select
D1
D0
Timeout of Internal RC OSC Timeout of System Clock
0
0
3.5 ms min
128 SCLK
0
1
7 ms min
256 SCLK
1
0
14 ms min
512 SCLK
1
1
56 ms min
2048 SCLK
Note: SCLK = system bus clock cycle. The default on RESET is 7 ms. Values provided are for V_CC
= 5.0V.
WDTMR During HALT (D2). This bit determines whether or not the WDT is active
during HALT mode. A 1 indicates active during HALT. The default is 1.
PS015601-1003