Z87C33 Datasheet, PDF (30/72 Pages) Zilog, Inc. – CMOS Z8® MCU Consumer Controller Processor

Z87C33
CMOS Z8“ MCU Consumer Controller Processor
24
Table 8. Stop-Mode Recovery Register 1—SMR1 0Bh/R11 Bank Fh: WRITE ONLY, except Bit D7,
which is READ ONLY
Reset
0
0
1
0
0
0
0
0
Note: R = Read, W = Write, X = Indeterminate.
Bit
Bit
Position Field
Reset
R/W State Description
D7
STP
R
0 Stop Flag
0: POR
1: Stop-Mode Recovery
D6
SMR
W
0 Stop-Mode Recovery Level
0: Low
1: High
D5
STPDLY
D4–D2 SMRSRC
W
1 Stop Delay
0: Off
1: On
W
000 Stop-Mode Recovery Source ¹
000: POR only and/or external RESET
001: P30
010: P31
011: P32
100: P33
101: P27
110: P2 NOR 0–3
111: P2 NOR 0–7
D1
EXTCLK
W
0 External Clock Divide-by-2
0: SCLK & TCLK = XTAL ÷ 2
1: SCLK & TCLK = XTAL
D0
CLK
W
0 SCLK & TCLK Divide-by-16
0: Off ²
1: On
Notes:
1. Do not use in conjunction with SMR2 Source.
2. Cleared by RESET and SMR.
SCLK & TCLK Divide-by-16 Select (D0). Bit D0 of the SMR controls a divide-by-16
prescaler of SCLK & TCLK. The purpose of this control is to selectively reduce
device power consumption during normal processor execution (SCLK control)
and/or HALT mode (where TCLK sources counter/timers and interrupt logic). This
bit is reset to D0 = 0 after a Stop-Mode Recovery.
PS015601-1003