Z87C33 Datasheet, PDF (32/72 Pages) Zilog, Inc. – CMOS Z8® MCU Consumer Controller Processor

Z87C33
CMOS Z8“ MCU Consumer Controller Processor
26
Table 9. Stop-Mode Recovery Source
SMR[4–2]
D4
D3
D2
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Operation/Description of Action
POR and/or external reset recovery
P30 transition
P31 transition (not in ANALOG mode)
P32 transition (not in ANALOG mode)
P33 transition (not in ANALOG mode)
P27 transition
Logical NOR of P20 through P23
Logical NOR of P20 through P27
Stop-Mode Recovery Delay Select (D5). This bit, if High, enables the T_POR RESET
delay after Stop-Mode Recovery. The default configuration of this bit is 1. If the
fast wake up (no delay) is selected, the Stop-Mode Recovery source must be kept
active for at least 5 T_PC. The clock source must be RC/LC/external clock driven.
Stop-Mode Recovery Edge Select (D6). A 1 in this bit position indicates that a high
level on any one of the recovery sources wakes the Z8 from STOP mode. A 0 indi-
cates low-level recovery. The default is 0 on POR (Table 11). This bit is used for
either SMR or SMR2.
Cold or Warm Start (D7). This bit is set by the device upon entering STOP mode. A
0 in this bit (cold) indicates that the device resets by POR/WDT RESET. A 1 in this
bit (warm) indicates that the device awakens by a Stop-Mode Recovery source.
Note: If the Port 2 pin is configured as an output, this output level is
read by the SMR2 circuitry.
Stop-Mode Recovery Register 2 (SMR2). This register contains additional Stop-
Mode Recovery sources. When the Stop-Mode Recovery sources are selected in
this register then SMR register bits D2, D3, and D4 must be 0.
Table 10. Stop-Mode Recovery Register 2
SMR1–0
D1
D0
0
0
Operation/Description of Action
POR and/or external reset recovery
PS015601-1003