Z87C33 Datasheet, PDF (33/72 Pages) Zilog, Inc. – CMOS Z8® MCU Consumer Controller Processor

Z87C33
CMOS Z8“ MCU Consumer Controller Processor
27
SMR1–0
D1
D0
0
1
1
0
Table 10. Stop-Mode Recovery Register 2
Operation/Description of Action
Logical AND of P20 through P23
Logical AND of P20 through P27
Table 11. Stop-Mode Recovery Register 2—SMR2 0Dh/R13 Bank Fh: WRITE ONLY
Bit
D7
D6 D5
D4
D3
D2
D1
D0
R/W
W
W
W
W
W
W
W
W
Reset
X
X
X
X
X
X
0
0
Note: R = Read, W = Write, X = Indeterminate.
Bit/ Bit
Field Position
Reset
R/W State Description
D7–D2 Reserved
W
X Reserved—must be 0
D1–D0 STOP Mode
W
00 Stop-Mode Recovery Source 2*
00: POR only
01: AND P20, P21, P22, P23
10: AND P20, P21, P22, P23, P24, P25,
P26, P27
11: Reserved
Note: *Do not use in conjunction with SMR Source.
Watch-Dog Timer Mode Register (WDTMR). The WDT is a retriggerable one-shot
timer that resets the Z8 if it reaches its terminal count. The WDT is initially enabled
by executing the WDT instruction and refreshed on subsequent executions of the
WDT instruction. The WDT circuit is driven by an onboard RC oscillator or exter-
nal oscillator from the X_IN pin. The POR clock source is selected with bit 4 of the
WDT register (Table 15).
WDT instruction affects the Z (Zero), S (Sign), and V (Overflow) flags. The
WDTMR must be written to within the first 60 internal system clocks. After that, the
WDTMR is WRITE-protected.
Note: WDT time-out while in STOP mode does not reset SMR, PCON,
WDTMR, P2M, P3M, Ports 2 & 3 Data Registers, but the POR
delay counter is still enabled even though the SMR stop delay is
disabled.
PS015601-1003