Z87C33 Datasheet, PDF (29/72 Pages) Zilog, Inc. – CMOS Z8® MCU Consumer Controller Processor

Z87C33
CMOS Z8“ MCU Consumer Controller Processor
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Low-EMI Port 2 (D5). Port 2 is configured as a low-EMI port by resetting this bit (D5
= 0) or configured as a Standard Port by setting this bit (D5 = 1). The default value
is 1.
Low-EMI Port 3 (D6). Port 3 is configured as a low-EMI port by resetting this bit (D6
= 0) or configured as a Standard Port by setting this bit (D6 = 1). The default value
is 1.
Low-EMI OSC (D7). This bit of the PCON register controls the low-EMI noise oscil-
lator. A 1 in this location configures the oscillator, DS, AS and R/W with standard
drive, while a 0 configures the oscillator, DS, AS and R/W with low noise drive.
LOW-EMI mode reduces the drive of the oscillator (OSC). The default value is 1.
Note: Maximum external clock frequency of 4 MHz when running in
LOW-EMI OSCILLATOR mode.
Low-EMI Emission. The Z8 is programmed to operate in a low-EMI emission mode
in the PCON register. The oscillator and all I/O ports is programmed as LOW-EMI
EMISSION mode independently. Use of this feature results in:
• The pre-drivers slew rate reduced to 10 ns (typical)
• Low-EMI output drivers exhibit resistance of 200Ω (typical)
• Low-EMI Oscillator
• Internal SCLK = X_IN operation limited to a maximum of 4 MHz–250 ns cycle time,
when LOW EMI OSCILLATOR is selected and system clock (SMR Register Bit
D1 = 1)
Stop-Mode Recovery Registers (SMR1 and SMR2). These registers select the clock
divide value and determine the mode of Stop-Mode Recovery (Tables 8 and 11).
All bits are WRITE ONLY, except bit 7 of SMR1, which is READ ONLY. SMR1 bit 7
is a flag bit that is set by hardware on a Stop-Mode Recovery condition and reset
by a power-on cycle. For SMR1, bit 6 controls whether a Low level or a High level
is required from the recovery source. Bit 5 controls the reset delay after Stop-
Mode Recovery. Bits 2, 3, and 4 of the SMR1 register specify the source of the
Stop-Mode Recovery signal. Bits 0 and 1 determine the time-out period of the
WDT. The SMR registers are located in Bank F of the Expanded Register File at
addresses 0Bh and 0Dh, respectively.
For SMR2, bits 7 to 2 are reserved. Bits 1 and 0 of the SMR2 register specify the
source of the Stop-Mode Recovery signal.
Table 8. Stop-Mode Recovery Register 1—SMR1 0Bh/R11 Bank Fh: WRITE ONLY, except Bit D7,
which is READ ONLY
Bit
R/W
D7
D6 D5
D4
D3
D2
D1
D0
R
W
W
W
W
W
W
W
PS015601-1003