YGV639 Datasheet, PDF (4/34 Pages) YAMAHA CORPORATION – Video Controller 1 with Enhanced Functions

YGV639
■ Block Diagram
Analog
Video Input
VINP
VINM
VREFP
VREFN
VREF0
Pattern
Memory I/F
MD15-0
MA25-0
MOE_N
MWE_N
RAHZ_N
CPU I/F
D7-0
PS2-0
CS_N
RD_N
WR_N
WAIT_N
READY_N
INT_N
SDIN
SDOUT
SCS_N
SCLK
SER_N
RESET_N
Analog
Front
End
CPU
Interface
Video
Decoder
Line
Buffer
(Video display
use)
Video
Signal
Controller
Sprite
&
Text
Rendering
Processor
Sprite & Text Plane Generator
Line Buffer
F
Frame Data
Controller
Macro
Command
module
Color Palette
General
Table
Registers
To all
blocks
Line Plane Generator
Line
Rendering
Processor
CRTC
To all
blocks
Clock
Gen.
Monitor I/F
DR5-0
DG5-0
DB5-0
HCSYNC_N
VSYNC_N
BLANK_N
DOTCLK
CLKV
STARTH
STARTV
LOADH
POL
OUTENV
TCONE
Clock
XIN
XOUT
DTCKIN
DTCKS_N
PLLCTL3-0
4