YGV639 Datasheet, PDF (13/34 Pages) YAMAHA CORPORATION – Video Controller 1 with Enhanced Functions

YGV639
CPU Interface
Although in VC1E either 8-bit asynchronous parallel or synchronous serial interface can be selected, pins
are shared by both interfaces.
CPU Data Bus
D7-0 (Input and Output)
When using 8-bit parallel interface, connect these pins to the CPU data bus. D7-0 serve as output pins
when both CS_N and RD_N pins are asserted (“L” level input), otherwise, it serves as input pins. Pull up
D7-0 pins outside the device as no pull-up resistors are provided.
When using the serial interface, input “H” or “L” level to the pins.
Port Select Pins
PS2-0 (Input)
Internal port selection pins. Connect the pins to the CPU address bus when 8-bit parallel interface is used.
When using VC1E in serial interface, input “H” or “L” level to the pins.
Chip Select Pin
CS_N (Input)
Chip-select input pin when 8-bit parallel interface is selected. WR_N and RD_N pins are enabled when
this signal is in active state. Connect CS_N pin to the CPU's chip select pin for external devices. This pin is
low active. This pin is a dual-purpose pin. When using the serial interface, it functions as SCS_N pin.
Read Strobe Input Pin
RD_N (Input)
Read Strobe Input Pin when 8-bit parallel interface is used. This pin is Low-active. This pin is a
dual-purpose pin. When using the serial interface, it functions as SDIN pin.
Write Strobe Input Pin
WR_N (Input)
Write Strobe Input Pin when 8-bit parallel interface is used. This pin is low active. This pin is a
dual-purpose pin. When using the serial interface, it functions as SCLK pin.
CPU Bus Wait Pin
WAIT_N (3-State Output)
The bus wait signal is output when 8-bit parallel interface is used. Use this pin and READY_N pin
properly depending on CPU. This pin is a 3-state output.
While “H” level is input to CS_N pin, it becomes a high impedance state. This pin is low active. Pull up
this pin outside the device as no pull-up resistor is provided. This pin is a dual-purpose pin. When using the
serial interface, it functions as SDOUT pin.
CPU Bus Ready Pin
READY_N (3-State Output)
The bus ready signal is output when 8-bit parallel interface is used. Use this pin and WAIT_N pin properly
depending on CPU. This pin is a 3-state output. While “H” level is input to CS_N pin, it becomes a high
impedance state. This pin is low active. Pull up READY_N pin outside the device as no pull-up resistor is
provided.
13